| 2009 |
|---|
| 8 | EE | JongHyuk Lee,
SungJin Song,
JoonMin Gil,
KwangSik Chung,
Taeweon Suh,
HeonChang Yu:
Balanced Scheduling Algorithm Considering Availability in Mobile Grid.
GPC 2009: 211-222 |
| 2008 |
|---|
| 7 | EE | Shih-Lien Lu,
Peter Yiannacouras,
Taeweon Suh,
Rolf Kassa,
Michael Konow:
A Desktop Computer with a Reconfigurable Pentium®.
TRETS 1(1): (2008) |
| 2007 |
|---|
| 6 | EE | Shih-Lien Lu,
Peter Yiannacouras,
Rolf Kassa,
Michael Konow,
Taeweon Suh:
An FPGA-based Pentium in a complete desktop system.
FPGA 2007: 53-59 |
| 5 | EE | Taeweon Suh,
Shih-Lien Lu,
Hsien-Hsin S. Lee:
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems.
FPL 2007: 47-53 |
| 2005 |
|---|
| 4 | EE | Taeweon Suh,
Daehyun Kim,
Hsien-Hsin S. Lee:
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.
DAC 2005: 553-558 |
| 2004 |
|---|
| 3 | EE | Taeweon Suh,
Douglas M. Blough,
Hsien-Hsin S. Lee:
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems.
DATE 2004: 1150-1157 |
| 2 | EE | Taeweon Suh,
Hsien-Hsin S. Lee,
Douglas M. Blough:
Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1.
IEEE Micro 24(4): 33-41 (2004) |
| 1 | EE | Taeweon Suh,
Hsien-Hsin S. Lee,
Douglas M. Blough:
Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2.
IEEE Micro 24(5): 70-78 (2004) |
