| 2009 |
|---|
| 10 | EE | Saurabh K. Tiwary,
Amith Singhee,
Vikas Chandra:
Robust Circuit Design: Challenges and Solutions.
VLSI Design 2009: 41-42 |
| 2008 |
|---|
| 9 | EE | Vikas Chandra,
Robert Aitken:
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS.
DFT 2008: 114-122 |
| 2005 |
|---|
| 8 | EE | Herman Schmit,
Vikas Chandra:
Layout techniques for FPGA switch blocks.
IEEE Trans. VLSI Syst. 13(1): 96-105 (2005) |
| 2004 |
|---|
| 7 | EE | Vikas Chandra,
Anthony Xu,
Herman Schmit,
Lawrence T. Pileggi:
An Interconnect Channel Design Methodology for High Performance Integrated Circuits.
DATE 2004: 1138-1143 |
| 6 | EE | Vikas Chandra,
Herman Schmit,
Anthony Xu,
Lawrence T. Pileggi:
A power aware system level interconnect design methodology for latency-insensitive systems.
ICCAD 2004: 275-282 |
| 5 | EE | Vikas Chandra,
Anthony Xu,
Herman Schmit:
A low power approach to system level pipelined interconnect design.
SLIP 2004: 45-52 |
| 2003 |
|---|
| 4 | EE | Aneesh Koorapaty,
Vikas Chandra,
K. Y. Tong,
Chetan Patel,
Lawrence T. Pileggi,
Herman Schmit:
Heterogeneous Programmable Logic Block Architectures.
DATE 2003: 11118-11119 |
| 3 | EE | Vikas Chandra,
Gary D. Carpenter,
Jeff Burns:
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs.
ICCD 2003: 134-139 |
| 2002 |
|---|
| 2 | EE | Herman Schmit,
Vikas Chandra:
FPGA switch block layout and evaluation.
FPGA 2002: 11-18 |
| 1 | EE | Vikas Chandra,
Herman Schmit:
Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach.
ISVLSI 2002: 35-40 |
