| 2009 |
|---|
| 10 | EE | Alexander Stempkovsky,
Alexey Glebov,
Sergey Gavrilov:
Calculation of stress probability for NBTI-aware timing analysis.
ISQED 2009: 714-718 |
| 2004 |
|---|
| 9 | EE | Alexey Glebov,
Sergey Gavrilov,
Vladimir Zolotov,
Chanhee Oh,
Rajendran Panda,
Murat R. Becer:
False-Noise Analysis for Domino Circuits.
DATE 2004: 784-789 |
| 8 | EE | Alexey Glebov,
Sergey Gavrilov,
R. Soloviev,
Vladimir Zolotov,
Murat R. Becer,
Chanhee Oh,
Rajendran Panda:
Delay noise pessimism reduction by logic correlations.
ICCAD 2004: 160-167 |
| 2003 |
|---|
| 7 | EE | D. Nadezhin,
Sergey Gavrilov,
Alexey Glebov,
Y. Egorov,
Vladimir Zolotov,
David Blaauw,
Rajendran Panda,
Murat R. Becer,
Alexandre Ardelea,
A. Patel:
SOI Transistor Model for Fast Transient Simulation.
ICCAD 2003: 120128 |
| 2002 |
|---|
| 6 | EE | Alexey Glebov,
Sergey Gavrilov,
David Blaauw,
Vladimir Zolotov,
Rajendran Panda,
Chanhee Oh:
False-Noise Analysis Using Resolution Method.
ISQED 2002: 437- |
| 5 | EE | Alexey Glebov,
Sergey Gavrilov,
David Blaauw,
Vladimir Zolotov:
False-noise analysis using logic implications.
ACM Trans. Design Autom. Electr. Syst. 7(3): 474-498 (2002) |
| 2001 |
|---|
| 4 | EE | Alexey Glebov,
Sergey Gavrilov,
David Blaauw,
Supamas Sirichotiyakul,
Chanhee Oh,
Vladimir Zolotov:
False-Noise Analysis using Logic Implications.
ICCAD 2001: 515- |
| 1997 |
|---|
| 3 | EE | Sergey Gavrilov,
Alexey Glebov,
S. Rusakov,
David Blaauw,
Larry G. Jones,
Gopalakrishnan Vijayan:
Fast power loss calculation for digital static CMOS circuits.
ED&TC 1997: 411-415 |
| 2 | EE | Sergey Gavrilov,
Alexey Glebov,
Satyamurthy Pullela,
S. C. Moore,
Abhijit Dharchoudhury,
Rajendran Panda,
Gopalakrishnan Vijayan,
David Blaauw:
Library-less synthesis for static CMOS combinational logic circuits.
ICCAD 1997: 658-662 |
| 1995 |
|---|
| 1 | EE | Alexey Glebov,
David Blaauw,
Larry G. Jones:
Transistor reordering for low power CMOS gates using an SP-BDD representation.
ISLPD 1995: 161-166 |
