ITC 1997:
Washington,
DC,
USA
Proceedings IEEE International Test Conference 1997, Washington, DC, USA, November 3-5, 1997.
IEEE Computer Society 1997, ISBN 0-7803-4209-7 BibTeX
@proceedings{DBLP:conf/itc/1997,
title = {Proceedings IEEE International Test Conference 1997, Washington,
DC, USA, November 3-5, 1997},
publisher = {IEEE Computer Society},
year = {1997},
isbn = {0-7803-4209-7},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Plenary
- James T. Healy:
Future Management of the Semiconductor Manufacturing Process.
10 BibTeX
- Colin Maunder:
Plug and Play or Plug and Pray: We Have a Right to Know It Will Work (Or Why It Won't).
11 BibTeX
Dynamic Current Testing
- Edward I. Cole Jr., Jerry M. Soden, Paiboon Tangyunyong, Patrick L. Candelaria, Richard W. Beegle, Daniel L. Barton, Christopher L. Henderson, Charles F. Hawkins:
Transient Power Supply Voltage (VDDT) Analysis for Detecting IC Defects.
23-31 BibTeX
- J. S. Beasley, S. Pour-Mozafari, D. Huggett, Alan W. Righter, C. J. Apodaca:
iDD Pulse Response Testing Applied to Complex CMOS ICs.
32-39 BibTeX
- James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan:
Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data.
40-49 BibTeX
Embedded Core Testing
ATE Hardware Improvements For High-Speed Test
MCM Systems Test
Unpowered Opens Lecture Series
IDDQ Testing
Progress On Standards And Benchmarks
Memory Test
Test Synthesis
Unpowered Opens Lecture Series
Microprocessor Test I
Diagnosis & Failure Analysis Lecture Series
Deterministic Bist
Components for MCMS:
Known-Good-Die and Substrates
Mixed-Signal Seminar:
Measurement Techniques
Microprocessor Test II
Diagnosis and Failure Analysis Lecture Series Panel
Design for Delay Test
Concurrent Checking
Mixed-Signal Seminar:
Measurements Using P1149.4
- Kenneth P. Parker, John E. McDermid, Rodney A. Browen, Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa:
Design, Fabrications and Use of Mixed-Signal IC Testability Structures.
489-498 BibTeX
- Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou:
Parasitic Effect Removal for Analog Measurement in P1149.4 Environment.
499-508 BibTeX
- José Machado da Silva, Ana C. Leão, José Silva Matos, José Carlos Alves:
Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 Infrastructure.
509-517 BibTeX
High-Performance Probes and Sockets
BIST and DFT Economics
On-Line Testing Techniques for VLSI
Defect Behavior,
Test Efficiency and Fault Model Extension
Mixed-Signal Seminar Panel:
On-Chip 1149.4,
What for?
Board-Level Test Methods
Software For New Test Strategies
Design-For-Test Topics
Sequential ATPG
Mixed-Signal Seminar:
BIST/DFT
Test Engineering Topics
Tools and Techniques for Defect Testing
Specialized BIST Generators
Advances in Digital Logic Diagnosis
Mixed-Signal Seminar:
Fault Modeling
New Frontiers in Test
Design Verification and Diagnosis
Delay Fault Testing
Test Language Standards
Advances in Probe Technology
Partial Scan Is Dead. Long Live Almost-Full Scan!
Ethics,
Professionalism,
And Accountability - Does it Exist in Test?
Vision Systems For Board Test:
Meeting Their Promise?
So What Is An Optimal Test Mix? A Discussion Of The SEMATECH Methods Experiment
Embedded Core Test Plug-N-Play:
Is It Achievable?
On-Line Testing,
Industrial Practice And Perspectives
Best Paper
Copyright © Sat May 16 23:26:42 2009
by Michael Ley (ley@uni-trier.de)
