2008 | ||
---|---|---|
36 | EE | Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang: A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
35 | EE | Chao-Wen Tzeng, Shi-Yu Huang: UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. IEEE Design & Test of Computers 25(2): 132-140 (2008) |
2007 | ||
34 | EE | Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang: RT-level vector selection for realistic peak power simulation. ACM Great Lakes Symposium on VLSI 2007: 576-581 |
2006 | ||
33 | EE | Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang: A network security processor design based on an integrated SOC design and test platform. DAC 2006: 490-495 |
32 | EE | Yu-Chiun Lin, Shi-Yu Huang: Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults. J. Electronic Testing 22(2): 151-159 (2006) |
2005 | ||
31 | EE | Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang: Power estimation starategies for a low-power security processor. ASP-DAC 2005: 367-371 |
30 | EE | Jheng-Syun Yang, Shi-Yu Huang: Quick Scan Chain Diagnosis Using Signal Profiling. ICCD 2005: 157-160 |
2004 | ||
29 | EE | Shi-Yu Huang: A Fading Algorithm For Sequential Fault Diagnosis. DFT 2004: 139-147 |
2003 | ||
28 | EE | Yu-Chiun Lin, Shi-Yu Huang: Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults. Asian Test Symposium 2003: 38-43 |
27 | EE | MingHung Lee, TingTing Hwang, Shi-Yu Huang: Decomposition of Extended Finite State Machine for Low Power Design. DATE 2003: 11152-11153 |
26 | EE | Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang: Combinational circuit fault diagnosis using logic emulation. ISCAS (5) 2003: 549-552 |
25 | EE | Shi-Yu Huang: A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis. J. Electronic Testing 19(2): 161-172 (2003) |
24 | EE | Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu: Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. J. Inf. Sci. Eng. 19(4): 571-587 (2003) |
2002 | ||
23 | EE | Shi-Yu Huang: Diagnosis Of Byzantine Open-Segment Faults. Asian Test Symposium 2002: 248- |
22 | EE | Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang: Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. DFT 2002: 117-128 |
21 | EE | Shi-Yu Huang: Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation. VTS 2002: 193-200 |
2001 | ||
20 | EE | Shi-Yu Huang: Towards the logic defect diagnosis for partial-scan designs. ASP-DAC 2001: 313-318 |
19 | EE | Shi-Yu Huang: On speeding up extended finite state machines using catalyst circuitry. ASP-DAC 2001: 583-588 |
18 | EE | Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang: A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium 2001: 103- |
17 | EE | Shi-Yu Huang: On Improving the Accuracy Of Multiple Defect Diagnosis. VTS 2001: 34-41 |
16 | EE | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: Verifying sequential equivalence using ATPG techniques. ACM Trans. Design Autom. Electr. Syst. 6(2): 244-275 (2001) |
2000 | ||
15 | EE | Shi-Yu Huang, Sudhakar M. Reddy: High Performance/Delay Testing. Asian Test Symposium 2000: 490- |
14 | EE | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer: AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49(5): 443-464 (2000) |
1999 | ||
13 | EE | Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai: Fault emulation: A new methodology for fault grading. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1487-1495 (1999) |
12 | EE | Shi-Yu Huang, Kwang-Ting Cheng: ErrorTracer: design error diagnosis based on fault simulation techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1341-1352 (1999) |
11 | EE | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: AutoFix: a hybrid tool for automatic logic rectification. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1376-1384 (1999) |
1998 | ||
10 | Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho: A Hybrid Power Model for RTL Power Estimation. ASP-DAC 1998: 551-556 | |
9 | EE | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu: Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC 1998: 632-637 |
1997 | ||
8 | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng: Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. ITC 1997: 974-981 | |
7 | EE | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: Incremental logic rectification. VTS 1997: 143-149 |
1996 | ||
6 | EE | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee: Compact Vector Generation for Accurate Power Simulation. DAC 1996: 161-164 |
5 | EE | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: Error Correction Based on Verification Techniques. DAC 1996: 258-261 |
4 | EE | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI 1996: 277- |
3 | EE | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee: A novel methodology for transistor-level power estimation. ISLPED 1996: 67-72 |
2 | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser: An ATPG-Based Framework for Verifying Sequential Equivalence. ITC 1996: 865-874 | |
1995 | ||
1 | EE | Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai: Fault emulation: a new approach to fault grading. ICCAD 1995: 681-686 |