A. L. Burress

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1999

3 EE Parag K. Lala, A. L. Burress: Self-Checking Logic Design for LUT-Based FPGAs. FPGA 1999: 253

2 EE Parag K. Lala, A. L. Burress: A technique for designing self-checking logic for FPGAs. ISCAS (1) 1999: 94-96

1997

1 A. L. Burress, Parag K. Lala: On-Line Testable Logic Desgin for FPGA Implementation. ITC 1997: 471-478

1999
3	EE	Parag K. Lala, A. L. Burress: Self-Checking Logic Design for LUT-Based FPGAs. FPGA 1999: 253
2	EE	Parag K. Lala, A. L. Burress: A technique for designing self-checking logic for FPGAs. ISCAS (1) 1999: 94-96
1997
1		A. L. Burress, Parag K. Lala: On-Line Testable Logic Desgin for FPGA Implementation. ITC 1997: 471-478

Coauthor Index

1 Parag K. Lala [1] [2] [3]