| 2008 |
|---|
| 9 | EE | Sriram Sambamurthy,
Jacob A. Abraham,
Raghuram S. Tupuri:
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits.
VLSI Design 2008: 521-526 |
| 2006 |
|---|
| 8 | EE | Sriram Sambamurthy,
Jacob A. Abraham,
Raghuram S. Tupuri:
Delay Constrained Register Transfer Level Dynamic Power Estimation.
PATMOS 2006: 36-46 |
| 2003 |
|---|
| 7 | EE | Vivekananda M. Vedula,
Jacob A. Abraham,
Jayanta Bhadra,
Raghuram S. Tupuri:
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.
J. Electronic Testing 19(2): 149-160 (2003) |
| 2002 |
|---|
| 6 | EE | Jacob A. Abraham,
Arun Krishnamachary,
Raghuram S. Tupuri:
A Comprehensive Fault Model for Deep Submicron Digital Circuits.
DELTA 2002: 360-364 |
| 2001 |
|---|
| 5 | EE | Arun Krishnamachary,
Jacob A. Abraham,
Raghuram S. Tupuri:
Timing Verification and Delay Test Generation for Hierarchical Designs.
VLSI Design 2001: 157-162 |
| 2000 |
|---|
| 4 | EE | Raghuram S. Tupuri,
Jacob A. Abraham,
Daniel G. Saab:
Hierarchical Test Generation for Systems On a Chip.
VLSI Design 2000: 198- |
| 1999 |
|---|
| 3 | EE | Raghuram S. Tupuri,
Arun Krishnamachary,
Jacob A. Abraham:
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor.
DAC 1999: 647-652 |
| 1997 |
|---|
| 2 | | Raghuram S. Tupuri,
Jacob A. Abraham:
A Novel Functional Test Generation Method for Processors Using Commercial ATPG.
ITC 1997: 743-752 |
| 1 | EE | Raghuram S. Tupuri,
Jacob A. Abraham:
A Novel Hierarchical Test Generation Method for Processors.
VLSI Design 1997: 540-541 |
