2008 |
22 | EE | Yukiya Miura,
Jiro Kato:
Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling.
DFT 2008: 491-499 |
21 | EE | Yukiya Miura:
Ramp Voltage Testing for Detecting Interconnect Open Faults.
IEICE Transactions 91-D(3): 700-705 (2008) |
20 | EE | Yukiya Miura,
Jiro Kato:
Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X - Y Zoning Method.
J. Electronic Testing 24(1-3): 223-233 (2008) |
2006 |
19 | EE | Masaki Hashizume,
Tomomi Nishida,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada,
Yukiya Miura:
Current Testable Design of Resistor String DACs.
DELTA 2006: 197-200 |
18 | EE | Yukiya Miura,
Jiro Kato:
Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics.
DFT 2006: 410-418 |
17 | EE | Yukiya Miura:
Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study.
J. Electronic Testing 22(4-6): 411-423 (2006) |
2005 |
16 | EE | Yukiya Miura:
Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test.
DFT 2005: 573-581 |
2004 |
15 | EE | Yukiya Miura:
Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method.
DFT 2004: 230-238 |
2003 |
14 | EE | Masaki Hashizume,
Teppei Takeda,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada,
Yukiya Miura,
Kozo Kinoshita:
A BIST Circuit for IDDQ Tests.
Asian Test Symposium 2003: 390-395 |
13 | EE | Yukiya Miura,
Daisuke Kato:
Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation.
DFT 2003: 279-286 |
2002 |
12 | EE | Yukiya Miura,
Shuichi Seno:
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits.
J. Electronic Testing 18(2): 109-120 (2002) |
2001 |
11 | EE | Teppei Takeda,
Masaki Hashizume,
Masahiro Ichimiya,
Hiroyuki Yotsuyanagi,
Yukiya Miura,
Kozo Kinoshita:
IDDQ Sensing Technique for High Speed IDDQ Testing.
Asian Test Symposium 2001: 111-116 |
2000 |
10 | EE | Arabi Keshk,
Yukiya Miura,
Kozo Kinoshita:
Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.
Asian Test Symposium 2000: 120-124 |
1999 |
9 | EE | Arabi Keshk,
Kozo Kinoshita,
Yukiya Miura:
Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits.
Asian Test Symposium 1999: 121-126 |
8 | EE | Arabi Keshk,
Kozo Kinoshita,
Yukiya Miura:
IDDQ Current Dependency on Test Vectors and Bridging Resistance.
Asian Test Symposium 1999: 158-163 |
7 | EE | Yukiya Miura,
Hiroshi Yamazaki:
A Low-Loss Built-In Current Sensor.
J. Electronic Testing 14(1-2): 39-48 (1999) |
1998 |
6 | EE | Masaki Hashizume,
Yukiya Miura,
Masahiro Ichimiya,
Takeomi Tamesada,
Kozo Kinoshita:
A High-Speed IDDQ Sensor for Low-Voltage ICs.
Asian Test Symposium 1998: 327- |
1997 |
5 | | Yukiya Miura:
An IDDQ Sensor Circuit for Low-Voltage ICs.
ITC 1997: 938-947 |
1996 |
4 | EE | Yukiya Miura:
Real-Time Current Testing for A/D Converters.
IEEE Design & Test of Computers 13(2): 34-41 (1996) |
1995 |
3 | | Yukiya Miura:
A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent Testing.
ITC 1995: 71-77 |
1994 |
2 | | Yukiya Miura,
Sachio Naito,
Kozo Kinoshita:
A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit.
ISCAS 1994: 77-80 |
1992 |
1 | | Yukiya Miura,
Kozo Kinoshita:
Circuit Design for Built-in Current Testing.
ITC 1992: 873-881 |