| |
| 1999 | ||
|---|---|---|
| 5 | R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma: A comparison of bridging fault simulation methods. ITC 1999: 587-595 | |
| 1998 | ||
| 4 | EE | R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma: Testability Features of the AMD-K6 Microprocessor. IEEE Design & Test of Computers 15(3): 64-69 (1998) |
| 1997 | ||
| 3 | R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma: Testability Features of AMD-K6TM Microprocessor. ITC 1997: 406-413 | |
| 1995 | ||
| 2 | EE | Imtiaz P. Shaik, Michael L. Bushnell: A graph approach to DFT hardware placement for robust delay fault BIST. VLSI Design 1995: 177-182 |
| 1 | EE | Imtiaz P. Shaik, Michael L. Bushnell: Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . VTS 1995: 393-399 |
| 1 | Michael L. Bushnell | [1] [2] |
| 2 | R. Scott Fetherston | [3] [4] [5] |
| 3 | Siyad C. Ma | [3] [4] [5] |