| 2004 |
|---|
| 11 | EE | Charles Njinda:
A Hierarchical DFT Architecture for Chip, Board and System Test/Debug.
ITC 2004: 1061-1071 |
| 1997 |
|---|
| 10 | EE | Rajesh Raina,
Robert Bailey,
Charles Njinda,
Robert F. Molyneaux,
Charlie Beh:
Efficient Testing of Clock Regenerator Circuits in Scan Designs.
DAC 1997: 95-100 |
| 9 | | Rajesh Raina,
Charles Njinda,
Robert F. Molyneaux:
How Seriously Do You Take Your Possible-Detect Faults?
ITC 1997: 819-828 |
| 1995 |
|---|
| 8 | | Charles Njinda,
Neeraj Kaul:
Performance Driven BIST Technique for Random Logic.
ITC 1995: 524-533 |
| 1994 |
|---|
| 7 | EE | Ishwar Parulkar,
Melvin A. Breuer,
Charles Njinda:
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST.
DAC 1994: 345-356 |
| 6 | EE | Kuen-Jong Lee,
Charles Njinda,
Melvin A. Breuer:
SWiTEST: a switch level test generation system for CMOS combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 625-637 (1994) |
| 1993 |
|---|
| 5 | EE | Sen-Pin Lin,
Charles Njinda,
Melvin A. Breuer:
Generating a family of testable designs using the BILBO methodology.
J. Electronic Testing 4(1): 71-89 (1993) |
| 1992 |
|---|
| 4 | EE | Kuen-Jong Lee,
Charles Njinda,
Melvin A. Breuer:
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits.
DAC 1992: 26-29 |
| 3 | | Sridhar Narayanan,
Charles Njinda,
Melvin A. Breuer:
Optimal Sequencing of Scan Registers.
ITC 1992: 293-302 |
| 1991 |
|---|
| 2 | | Debaditya Mukherjee,
Charles Njinda,
Melvin A. Breuer:
Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware.
ICCAD 1991: 236-239 |
| 1 | | Sen-Pin Lin,
Charles Njinda,
Melvin A. Breuer:
A Systematic Approach for Designing Testable VLSI Circuits.
ICCAD 1991: 496-499 |
