| 2001 |
|---|
| 11 | EE | Yue-Tsang Chen,
Chauchin Su:
Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization.
VTS 2001: 260-265 |
| 10 | EE | Chauchin Su,
Yue-Tsang Chen,
Shyh-Jye Jou:
Intrinsic response for analog module testing using an analog testability bus.
ACM Trans. Design Autom. Electr. Syst. 6(2): 226-243 (2001) |
| 2000 |
|---|
| 9 | EE | Chauchin Su,
Yue-Tsang Chen,
Mu-Jeng Huang,
Gen-Nan Chen,
Chung-Len Lee:
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses.
DATE 2000: 527- |
| 8 | EE | Chauchin Su,
Yue-Tsang Chen:
Crosstalk Effect Removal for Analog Measurement in Analog Test Bus.
VTS 2000: 403-410 |
| 7 | EE | Chauchin Su,
Yue-Tsang Chen:
Intrinsic response extraction for the removal of the parasiticeffects in analog test buses.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 437-445 (2000) |
| 6 | EE | Chauchin Su,
Yue-Tsang Chen,
Shenshung Chiang:
Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis.
J. Inf. Sci. Eng. 16(5): 767-781 (2000) |
| 1999 |
|---|
| 5 | EE | Chauchin Su,
Yue-Tsang Chen,
Chung-Len Lee:
Analog Metrology and Stimulus Selection in a Noisy Environment.
Asian Test Symposium 1999: 233-238 |
| 1998 |
|---|
| 4 | EE | Chauchin Su,
Shung-Won Jeng,
Yue-Tsang Chen:
Boundary scan BIST methodology for reconfigurable systems.
ITC 1998: 774-783 |
| 1997 |
|---|
| 3 | EE | Chauchin Su,
Yi-Ren Cheng,
Yue-Tsang Chen,
Shing Tenchen:
Analog signal metrology for mixed signal ICs.
Asian Test Symposium 1997: 194- |
| 2 | | Chauchin Su,
Yue-Tsang Chen,
Shyh-Jye Jou:
Parasitic Effect Removal for Analog Measurement in P1149.4 Environment.
ITC 1997: 499-508 |
| 1996 |
|---|
| 1 | EE | Chauchin Su,
Yue-Tsang Chen,
Shyh-Jye Jou,
Yuan-Tzu Ting:
Metrology for analog module testing using analog testability bus.
ICCAD 1996: 594-599 |
