2008 |
24 | EE | Jyun-Nan Lin,
Hsiao-Yun Chen,
Ting-Chen Wei,
Shyh-Jye Jou:
Symbol and carrier frequency offset synchronization for IEEE802.16e.
ISCAS 2008: 3082-3085 |
23 | EE | Li-Rong Wang,
Yi-Wei Chiu,
Chia-Lin Hu,
Ming-Hsien Tu,
Shyh-Jye Jou,
Chung-Len Lee:
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library.
ISCAS 2008: 3426-3429 |
2007 |
22 | EE | Wei-Chang Liu,
Ting-Chen Wei,
Shyh-Jye Jou:
Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H.
ISCAS 2007: 2092-2095 |
2006 |
21 | EE | Ting-Zhen Wei,
Shyh-Jye Jou,
Muh-Tian Shiue:
Memory reduction ICFO estimation architecture for DVB-T.
ISCAS 2006 |
2005 |
20 | EE | Shyh-Jye Jou,
Chih-Hsien Lin,
Yen-I Wang:
A 12.5 Gbps CMOS input sampler for serial link receiver front end.
ISCAS (2) 2005: 1055-1058 |
19 | EE | Chih-Hsien Lin,
Chang-Hsiao Tsai,
Chih-Ning Chen,
Shyh-Jye Jou:
Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link.
IEICE Transactions 88-C(10): 2009-2019 (2005) |
2004 |
18 | EE | Chih-Hsien Lin,
Chang-Hsiao Tsai,
Chih-Ning Chen,
Shyh-Jye Jou:
4/2 PAM serial link transmitter with tunable pre-emphasis.
ISCAS (1) 2004: 952-958 |
17 | | Kai-Yuan Jheng,
Shyh-Jye Jou,
An-Yeu Wu:
A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code.
ISCAS (5) 2004: 293-296 |
2003 |
16 | EE | Ya-Lan Tsao,
Ming Hsuan Tan,
Jun-Xian Teng,
Shyh-Jye Jou:
Parameterized and low power DSP core for embedded systems.
ISCAS (5) 2003: 265-268 |
2002 |
15 | EE | Meng-Hung Tsai,
Yi-Ting Chen,
Wen-Sheng Cheng,
Jun-Xian Teng,
Shyh-Jye Jou:
Sub-word and reduced-width Booth multipliers for DSP applications.
ISCAS (3) 2002: 575-578 |
14 | EE | Shyh-Jye Jou,
Hsiao Ping Lee,
Yi-Ting Chen,
Ming Hsuan Tan,
Ya-Lan Tsao:
An embedded DSP core for wireless communication.
ISCAS (4) 2002: 524-527 |
2001 |
13 | EE | Maw-Ching Liu,
Chien-Lung Chen,
Ding-Yu Shin,
Chin-Hung Lin,
Shyh-Jye Jou:
Low-power multiplierless FIR filter synthesizer based on CSD code.
ISCAS (4) 2001: 666-669 |
12 | EE | Shyh-Jye Jou,
Shu-Hua Kuo,
Jui-Ta Chiu,
Chu King,
Chien-Hsiung Lee,
Tim Liu:
A serial link transceiver for USB2 high-speed mode.
ISCAS (4) 2001: 72-75 |
11 | EE | Chauchin Su,
Yue-Tsang Chen,
Shyh-Jye Jou:
Intrinsic response for analog module testing using an analog testability bus.
ACM Trans. Design Autom. Electr. Syst. 6(2): 226-243 (2001) |
2000 |
10 | EE | Shyh-Jye Jou,
Hui-Hsuan Wang:
Fixed-Width Multiplier for DSP Application.
ICCD 2000: 318-322 |
1999 |
9 | EE | Chauchin Su,
Shyh-Jye Jou:
Decentralized BIST Methodology for System Level Interconnects.
J. Electronic Testing 15(3): 255-265 (1999) |
1997 |
8 | | Chauchin Su,
Yue-Tsang Chen,
Shyh-Jye Jou:
Parasitic Effect Removal for Analog Measurement in P1149.4 Environment.
ITC 1997: 499-508 |
1996 |
7 | EE | Chauchin Su,
Shyh-Shen Hwang,
Shyh-Jye Jou,
Yuan-Tzu Ting:
Syndrome Simulation And Syndrome Test For Unscanned Interconnects.
Asian Test Symposium 1996: 62-67 |
6 | EE | Chauchin Su,
Yue-Tsang Chen,
Shyh-Jye Jou,
Yuan-Tzu Ting:
Metrology for analog module testing using analog testability bus.
ICCAD 1996: 594-599 |
1995 |
5 | EE | Chauchin Su,
Shenshung Chiang,
Shyh-Jye Jou:
Impulse response fault model and fault extraction for functional level analog circuit diagnosis.
ICCAD 1995: 631-636 |
4 | | Shyh-Jye Jou,
Kou-Fong Liu,
Chauchin Su:
Circuits Design Optimization Using Symbolic Approach.
ISCAS 1995: 1396-1399 |
3 | | Wen-Hsing Hsieh,
Shyh-Jye Jou,
Chauchin Su:
A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors.
ISCAS 1995: 574-577 |
1994 |
2 | | Shyh-Jye Jou,
Mei-Fang Perng,
Chauchin Su,
C. K. Wang:
Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits.
ISCAS 1994: 21-24 |
1 | | Chauchin Su,
Kychin Hwang,
Shyh-Jye Jou:
An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment.
ITC 1994: 670-676 |