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Masaaki Yoshida

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2006
4EEHirotaka Komoda, Masaaki Yoshida, Yoh Yamamoto, Kouji Iwasaki, Ikuko Nakatani, Heiji Watanabe, Kiyoshi Yasutake: Novel charge neutralization techniques applicable to wide current range of FIB processing in FIB-SEM combined system. Microelectronics Reliability 46(12): 2085-2095 (2006)
1997
3EEToshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida: Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs. Asian Test Symposium 1997: 122-125
2 Toshiharu Asaka, Masaaki Yoshida, Subhrajit Bhattacharya, Sujit Dey: H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs. ITC 1997: 265-274
1991
1 Toshinobu Ono, Masaaki Yoshida: A Test Generation Method for Sequential Circuits Based on Maximum Utilization of Internal States. ITC 1991: 75-82

Coauthor Index

1Toshiharu Asaka [2]
2Subhrajit Bhattacharya [2]
3Sujit Dey [2]
4Hitoshi Hikima [3]
5Kouji Iwasaki [4]
6Hirotaka Komoda [4]
7Yoshiyuki Nakamura [3]
8Ikuko Nakatani [4]
9Toshinobu Ono [1] [3]
10Kazuo Wakui [3]
11Heiji Watanabe [4]
12Yoh Yamamoto [4]
13Kiyoshi Yasutake [4]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)