2005 |
17 | EE | Ruchir Puri,
Leon Stok,
Subhrajit Bhattacharya:
Keeping hot chips cool.
DAC 2005: 285-288 |
16 | EE | Subhrajit Bhattacharya,
John A. Darringer,
Daniel L. Ostapko,
Youngsoo Shin:
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost.
ISQED 2005: 482-487 |
15 | EE | Martin Ohmacht,
Reinaldo A. Bergamaschi,
Subhrajit Bhattacharya,
Alan Gara,
Mark Giampapa,
Balaji Gopalsamy,
Ruud A. Haring,
Dirk Hoenicke,
David J. Krolak,
James A. Marcella,
Ben J. Nathanson,
Valentina Salapura,
Michael E. Wazlowski:
Blue Gene/L compute chip: Memory and Ethernet subsystem.
IBM Journal of Research and Development 49(2-3): 255-264 (2005) |
2003 |
14 | EE | Reinaldo A. Bergamaschi,
Youngsoo Shin,
Nagu R. Dhanwada,
Subhrajit Bhattacharya,
William E. Dougherty,
Indira Nair,
John A. Darringer,
Sarala Paliwal:
SEAS: a system for early analysis of SoCs.
CODES+ISSS 2003: 150-155 |
2002 |
13 | EE | John A. Darringer,
Reinaldo A. Bergamaschi,
Subhrajit Bhattacharya,
Daniel Brand,
Andreas Herkersdorf,
Joseph K. Morrell,
Indira Nair,
Patricia Sagmeister,
Youngsoo Shin:
Early analysis tools for system-on-a-chip design.
IBM Journal of Research and Development 46(6): 691-708 (2002) |
2001 |
12 | EE | Reinaldo A. Bergamaschi,
Subhrajit Bhattacharya,
Ronoldo Wagner,
Colleen Fellenz,
Michael Muhlada,
William R. Lee,
Foster White,
Jean-Marc Daveau:
Automating the Design of SOCs Using Cores.
IEEE Design & Test of Computers 18(5): 32-45 (2001) |
1999 |
11 | EE | Pranav Ashar,
Anand Raghunathan,
Aarti Gupta,
Subhrajit Bhattacharya:
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.
ICCD 1999: 458-466 |
1998 |
10 | EE | Pranav Ashar,
Subhrajit Bhattacharya,
Anand Raghunathan,
Akira Mukaiyama:
Verification of RTL generated from scheduled behavior in a high-level synthesis flow.
ICCAD 1998: 517-524 |
9 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization.
ACM Trans. Design Autom. Electr. Syst. 3(2): 285-307 (1998) |
1997 |
8 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Bhaskar Sengupta:
An RTL methodology to enable low overhead combinational testing.
ED&TC 1997: 146-152 |
7 | | Toshiharu Asaka,
Masaaki Yoshida,
Subhrajit Bhattacharya,
Sujit Dey:
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs.
ITC 1997: 265-274 |
1996 |
6 | EE | Subhrajit Bhattacharya,
Sujit Dey:
H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.
VTS 1996: 74-80 |
5 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Fast true delay estimation during high level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1088-1105 (1996) |
1994 |
4 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Clock Period Optimization During Resource Sharing and Assignment.
DAC 1994: 195-200 |
3 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications.
DAC 1994: 491-496 |
2 | EE | Subhrajit Bhattacharya,
Sujit Dey,
Franc Brglez:
Provably correct high-level timing analysis without path sensitization.
ICCAD 1994: 736-742 |
1993 |
1 | EE | Subhrajit Bhattacharya,
Franc Brglez,
Sujit Dey:
Transformations and resynthesis for testability of RT-level control-data path specifications.
IEEE Trans. VLSI Syst. 1(3): 304-318 (1993) |