| 2009 |
|---|
| 10 | EE | Hiroaki Yoshida,
Masahiro Fujita:
Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences.
ISQED 2009: 366-370 |
| 2008 |
|---|
| 9 | EE | Hiroaki Yoshida,
Masahiro Fujita:
Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits.
DATE 2008: 1099-1102 |
| 8 | | Masahiro Fujita,
Takeshi Matsumoto,
Hiroaki Yoshida:
A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams.
ICSOFT (SE/MUSE/GSDCA) 2008: 240-245 |
| 2007 |
|---|
| 7 | EE | Fujine Yano,
Hiroaki Yoshida:
Some set partition statistics in non-crossing partitions and generating functions.
Discrete Mathematics 307(24): 3147-3160 (2007) |
| 2006 |
|---|
| 6 | EE | Hiroaki Yoshida,
Makoto Ikeda,
Kunihiro Asada:
A Structural Approach for Transistor Circuit Synthesis.
IEICE Transactions 89-A(12): 3529-3537 (2006) |
| 2005 |
|---|
| 5 | EE | Ulkuhan Ekinciel,
Hiroaki Yamaoka,
Hiroaki Yoshida,
Makoto Ikeda,
Kunihiro Asada:
A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells.
IEICE Transactions 88-D(6): 1159-1167 (2005) |
| 2004 |
|---|
| 4 | EE | Hiroaki Yoshida,
Kaushik De,
Vamsi Boppana:
Accurate pre-layout estimation of standard cell characteristics.
DAC 2004: 208-211 |
| 2002 |
|---|
| 3 | | Mayumi Oto,
Masami Takata,
Hiroaki Yoshida,
Kazuki Joe:
A Quantum Algorithm for Searching Web Communities.
PDPTA 2002: 260-268 |
| 2 | EE | Hiroaki Yoshida,
Hiroaki Yamaoka,
Makoto Ikeda,
Kunihiro Asada:
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA.
VLSI Design 2002: 166-171 |
| 1 | EE | Hiroaki Yoshida,
Motohiro Sera,
Masao Kubo,
Masahiro Fujita:
Simultaneous Circuit Transformation and Routing.
VLSI Design 2002: 479-483 |
