| 2008 |
|---|
| 20 | EE | Xin Li,
Daryl Shannon,
Indradeep Ghosh,
Mizuhito Ogawa,
Sreeranga P. Rajan,
Sarfraz Khurshid:
Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution.
APLAS 2008: 36-52 |
| 2007 |
|---|
| 19 | EE | Oksana Tkachuk,
Sreeranga P. Rajan:
Combining environment generation and slicing for modular software model checking.
ASE 2007: 401-404 |
| 2006 |
|---|
| 18 | EE | Oksana Tkachuk,
Sreeranga P. Rajan:
Application of automated environment generation to commercial software.
ISSTA 2006: 203-214 |
| 17 | EE | Graham Hughes,
Sreeranga P. Rajan,
Tom Sidle,
Keith Swenson:
Error Detection in Concurrent Java Programs.
Electr. Notes Theor. Comput. Sci. 144(3): 45-58 (2006) |
| 16 | EE | David W. Currie,
Xiushan Feng,
Masahiro Fujita,
Alan J. Hu,
Mark Kwan,
Sreeranga P. Rajan:
Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions.
International Journal of Parallel Programming 34(1): 61-91 (2006) |
| 2005 |
|---|
| 15 | EE | Sreeranga P. Rajan:
Editorial.
TOS 1(1): 1-2 (2005) |
| 2002 |
|---|
| 14 | EE | Subir K. Roy,
S. Ramesh,
Supratik Chakraborty,
Tsuneo Nakata,
Sreeranga P. Rajan:
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).
VLSI Design 2002: 11-13 |
| 13 | EE | Edmund M. Clarke,
Masahiro Fujita,
Sreeranga P. Rajan,
Thomas W. Reps,
Subash Shankar,
Tim Teitelbaum:
Program slicing for VHDL.
STTT 4(1): 125-137 (2002) |
| 2001 |
|---|
| 12 | EE | Subramanian Rajagopalan,
Sreeranga P. Rajan,
Sharad Malik,
Sandro Rigo,
Guido Araujo,
Koichiro Takayama:
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1319-1328 (2001) |
| 2000 |
|---|
| 11 | EE | David W. Currie,
Alan J. Hu,
Sreeranga P. Rajan:
Automatic formal verification of DSP software.
DAC 2000: 130-135 |
| 1999 |
|---|
| 10 | EE | Vamsi Boppana,
Sreeranga P. Rajan,
Koichiro Takayama,
Masahiro Fujita:
Model Checking Based on Sequential ATPG.
CAV 1999: 418-430 |
| 9 | EE | Edmund M. Clarke,
Masahiro Fujita,
Sreeranga P. Rajan,
Thomas W. Reps,
Subash Shankar,
Tim Teitelbaum:
Program Slicing of Hardware Description Languages.
CHARME 1999: 298-312 |
| 8 | EE | Sreeranga P. Rajan,
Masahiro Fujita,
Ashok Sudarsanam,
Sharad Malik:
Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor.
CODES 1999: 2-6 |
| 1998 |
|---|
| 7 | | Masahiro Fujita,
Sreeranga P. Rajan,
Alan J. Hu:
Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol.
FM-Trends 1998: 281-295 |
| 6 | EE | Sreeranga P. Rajan,
Masahiro Fujita:
Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design.
VLSI Design 1998: 552-557 |
| 5 | EE | Sreeranga P. Rajan,
Masahiro Fujita,
K. Yuan,
Mike Tien-Chien Lee:
ATM switch design by high-level modeling, formal verification and high-level synthesi.
ACM Trans. Design Autom. Electr. Syst. 3(4): 554-562 (1998) |
| 1997 |
|---|
| 4 | | Sreeranga P. Rajan,
Masahiro Fujita:
ATM Switch Design: Parametric High-Level Modeling and Formal Verification.
AMAST 1997: 437-450 |
| 1996 |
|---|
| 3 | EE | Peter F. A. Middelhoek,
Sreeranga P. Rajan:
From VHDL to efficient and first-time-right designs: a formal approach.
ACM Trans. Design Autom. Electr. Syst. 1(2): 205-250 (1996) |
| 1993 |
|---|
| 2 | | Sreeranga P. Rajan,
Jeffrey J. Joyce,
Carl-Johan H. Seger:
From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation.
HUG 1993: 489-500 |
| 1992 |
|---|
| 1 | | Sreeranga P. Rajan:
Executing HOL Specifications: Towards an Evaluation Semantics for Classical Higher Order Logic.
TPHOLs 1992: 527-536 |
