Yoshikazu Miyanaga

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27EEShingo Yoshizawa, Kazuto Nishi, Yoshikazu Miyanaga: Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems. ISCAS 2008: 1248-1251
26EEShingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga: A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver. ISCAS 2008: 2486-2489
25EERhandley D. Cajote, Supavadee Aramvith, Rowena Cristina L. Guevara, Yoshikazu Miyanaga: FMO slice group maps using spatial and temporal indicators for H.264 wireless video transmission. ISCAS 2008: 3566-3569
24EEXin Xu, Noboru Hayasaka, Yoshikazu Miyanaga: Robust Speech Spectra Restoration against Unspecific Noise Conditions for Pitch Detection. IEICE Transactions 91-A(3): 775-781 (2008)
23EEShingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga: VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 x 4 MIMO-OFDM Receiver. IEICE Transactions 91-A(7): 1757-1762 (2008)
22EETakayuki Sugawara, Shingo Yoshizawa, Yoshikazu Miyanaga: Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems. ISCAS 2007: 2287-2290
21EEShingo Yoshizawa, Yoshikazu Miyanaga: Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation. ISCAS 2007: 3175-3178
20EEShingo Yoshizawa, Yoshikazu Miyanaga: VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System. APCCAS 2006: 93-96
19EEShingo Yoshizawa, Yoshikazu Miyanaga, H. Ochi, Y. Itoh, N. Hataoka, B. Sai, N. Takayama, M. Hirata: 300-Mbps OFDM baseband transceiver for wireless LAN systems. ISCAS 2006
18EENaoya Wada, Noboru Hayasaka, Shingo Yoshizawa, Yoshikazu Miyanaga: Direct control on modulation spectrum for noise-robust speech recognition and spectral subtraction. ISCAS 2006
17EENoboru Hayasaka, Yoshikazu Miyanaga: Spectrum filtering with FRM for robust speech recognition. ISCAS 2006
16EEShingo Yoshizawa, Yoshikazu Miyanaga: Tunable word length architecture for low power wireless OFDM demodulator. ISCAS 2006
15EEShingo Yoshizawa, Yoshikazu Miyanaga: Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator. IEICE Transactions 89-A(10): 2866-2873 (2006)
14EEKazuma Fujioka, Noboru Hayasaka, Yoshikazu Miyanaga, Norinobu Yoshida: Noise reduction of speech signals by running spectrum filtering. Systems and Computers in Japan 37(14): 52-61 (2006)
13EEYasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga: Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder. ISCAS (1) 2005: 25-28
12EEQi Zhu, Noriyuki Ohtsuki, Yoshikazu Miyanaga, Norinobu Yoshida: Noise-Robust Speech Analysis Using Running Spectrum Filtering. IEICE Transactions 88-A(2): 541-548 (2005)
11EEShingo Yoshizawa, Naoya Wada, Noboru Hayasaka, Yoshikazu Miyanaga: Scalable architecture for word HMM-based speech recognition. ISCAS (3) 2004: 417-420
10EETakayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yoshida: A Design of Analog C-Matrix Circuits Used for Signal/Data Processing. VLSI Design 2002: 355-359
9EEH. Ryu, Yoshikazu Miyanaga, Koji Tochinai: An image compression using self-organization with genetic algorithm. ISCAS (4) 1999: 5-8
8EEHiroshi Echizen-ya, Kenji Araki, Yoshikazu Miyanaga, Koji Tochinai: An Improvement in the Selection Process of Machine Translation Using Inductive Learning with Genetic Algorithms. ANLP 1997: 11-12
7 Honglan Jin, Yoshikazu Miyanaga, Koji Tochinai: Design of a Compact Cluster Structure by Using Genetic Algorithms. ISCAS 1995: 1512-1515
6 Rafiqul Islam, Makoto Hiroshige, Yoshikazu Miyanaga, Koji Tochinai: Phoneme Recognition System Based on a Modified TDNN Using Self-Organizing Clustering Network. ISCAS 1995: 1816-1819
5 Yoshikazu Miyanaga, Honglan Jin, Rafiqul Islam, Koji Tochinai: A Self-Organized Network with a Supervised Training. ISCAS 1995: 482-485
4 Jun'ya Shimizu, Yoshikazu Miyanaga, Koji Tochinai: An Estimation of Time-Varying Parameters using Multi-AR Lattice Models in Subbands. ISCAS 1994: 245-248
3 Frederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai: A Performance-driven Approach to the High-level Synthesis of DSP Algorithms. ISCAS 1993: 1658-1661
2 Yoshikazu Miyanaga, Takeshi Nagae, Tateo Shimozawa, Koji Tochinai: Neuron architecture based on jamming avoidance response of an electric fish. ISCAS 1993: 2600-2603
1EEFrederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai: An optimization technique for lowering the iteration bound of DSP programs. VLSI Signal Processing 5(2-3): 273-282 (1993)

Coauthor Index

1Kenji Araki [8]
2Supavadee Aramvith [25]
3Rhandley D. Cajote [25]
4Hiroshi Echizen-ya [8]
5Kazuma Fujioka [14]
6Rowena Cristina L. Guevara [25]
7Yasuyuki Hatakawa [13]
8N. Hataoka [19]
9Noboru Hayasaka [11] [14] [17] [18] [24]
10M. Hirata [19]
11Makoto Hiroshige [6]
12Rafiqul Islam [5] [6]
13Y. Itoh [19]
14Honglan Jin [5] [7]
15Frederico Buchholz Maciel [1] [3]
16Takeshi Nagae [2]
17Kazuto Nishi [27]
18H. Ochi [19]
19Noriyuki Ohtsuki [12]
20H. Ryu [9]
21B. Sai [19]
22Jun'ya Shimizu [4]
23Tateo Shimozawa [2]
24Takayuki Sugawara [10] [22]
25N. Takayama [19]
26Koji Tochinai [1] [2] [3] [4] [5] [6] [7] [8] [9]
27Naoya Wada [11] [18]
28Xin Xu [24]
29Yasushi Yamauchi [23] [26]
30Norinobu Yoshida [10] [12] [14]
31Shingo Yoshizawa [11] [13] [15] [16] [18] [19] [20] [21] [22] [23] [26] [27]
32Qi Zhu [12]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)