Ajit Pal

2009
19	EE	Ajit Pal, Santanu Chattopadhyay: Synthesis & Testing for Low Power. VLSI Design 2009: 37-38
2008
18	EE	Tanmay De, Ajit Pal, Indranil Sengupta: Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning. ICDCN 2008: 452-463
2007
17	EE	Akepati Sravan, Sujan Kundu, Ajit Pal: Low Power Sensor Node for a Wireless Sensor Network. VLSI Design 2007: 445-450
2006
16	EE	Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya: On finding the minimum test set of a BDD-based circuit. ACM Great Lakes Symposium on VLSI 2006: 169-172
15	EE	Gopal Paul, S. N. Pradhan, Ajit Pal, Bhargab B. Bhattacharya: Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. APCCAS 2006: 1504-1507
2005
14		Ajit Pal, Ajay D. Kshemkalyani, Rajeev Kumar, Arobinda Gupta: Distributed Computing - IWDC 2005, 7th International Workshop, Kharagpur, India, December 27-30, 2005, Proceedings Springer 2005
2004
13	EE	Ajit Pal, Umesh Patel: Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks. IWDC 2004: 391-396
12	EE	Maitrali Marik, Ajit Pal: Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. VLSI Design 2004: 73-78
11	EE	Debasis Samanta, Ajit Pal: Synthesis of Low Power High Performance Dual-VT PTL Circuits. VLSI Design 2004: 85-
2003
10	EE	Debasis Samanta, Ajit Pal: Synthesis of Dual-VT Dynamic CMOS Circuits. VLSI Design 2003: 303-308
2002
9	EE	Debasis Samanta, Ajit Pal: Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. VLSI Design 2002: 193-198
8	EE	Debasis Samanta, Nishant Sinha, Ajit Pal: Synthesis of High Performance Low Power Dynamic CMOS Circuits. VLSI Design 2002: 99-104
2001
7	EE	Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal: Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. VLSI Design 2001: 227-
1998
6	EE	Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal: An algorithm for finding a non-trivial lower bound for channel routing1. Integration 25(1): 71-84 (1998)
1997
5	EE	Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal: An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing. VLSI Design 1997: 531-533
1995
4	EE	Rajat K. Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal: Computing area and wire length efficient routes for channels. VLSI Design 1995: 196-201
3	EE	Rajat K. Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal: A general graph theoretic framework for multi-layer channel routing. VLSI Design 1995: 202-207
1993
2		Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta: NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic. VLSI Design 1993: 80-83
1986
1		Ajit Pal: An Algorithm for Optimal Logic Design Using Multiplexers. IEEE Trans. Computers 35(8): 755-757 (1986)

Coauthor Index

1	Bhargab B. Bhattacharya	[15] [16]
2	Amit M. Bhosle	[7]
3	Santanu Chattopadhyay	[19]
4	M. M. Das	[3] [4]
5	A. K. Datta	[3]
6	Tanmay De	[18]
7	Alak K. Dutta	[2]
8	Arobinda Gupta	[14]
9	Ajay D. Kshemkalyani	[14]
10	Rajeev Kumar	[14]
11	Sujan Kundu	[17]
12	Maitrali Marik	[12]
13	Rajat K. Pal	[2] [3] [4] [5] [6]
14	Sudebkumar Prasant Pal	[2] [3] [4] [5] [6]
15	Umesh Patel	[13]
16	Gopal Paul	[15] [16]
17	S. N. Pradhan	[15]
18	Debasis Samanta	[7] [8] [9] [10] [11]
19	Indranil Sengupta	[18]
20	Nishant Sinha	[8]
21	Akepati Sravan	[17]
22	Nikhil Tripathi	[7]

Colors in the list of coauthors