Maurizio Palesi

2009
35	EE	Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: Application Specific Routing Algorithms for Networks on Chip. IEEE Trans. Parallel Distrib. Syst. 20(3): 316-330 (2009)
2008
34	EE	Rafael Tornero, Juan M. Orduña, Maurizio Palesi, José Duato: A Communication-Aware Topological Mapping Technique for NoCs. Euro-Par 2008: 910-919
33	EE	Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. NOCS 2008: 97-106
32	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Trans. Computers 57(6): 809-820 (2008)
31	EE	Rickard Holsmark, Maurizio Palesi, Shashi Kumar: Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 427-440 (2008)
30	EE	Vincenzo Catania, Maurizio Palesi, Davide Patti: Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems. TACO 5(2): (2008)
2007
29	EE	Alessandro G. Di Nuovo, Maurizio Palesi, Vincenzo Catania: Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. FUZZ-IEEE 2007: 1-6
28	EE	Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania: Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IPDPS 2007: 1-8
27	EE	Vincenzo Catania, Maurizio Palesi, Davide Patti: Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario. Journal of Circuits, Systems, and Computers 16(5): 819-846 (2007)
26	EE	Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: Efficient design space exploration for application specific systems-on-a-chip. Journal of Systems Architecture 53(10): 733-750 (2007)
2006
25	EE	Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: A methodology for design of application specific deadlock-free routing algorithms for NoC systems. CODES+ISSS 2006: 142-147
24	EE	Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania: Fuzzy decision making in embedded system design. CODES+ISSS 2006: 223-228
23	EE	Rickard Holsmark, Maurizio Palesi, Shashi Kumar: Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. DSD 2006: 696-703
22	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. ESTImedia 2006: 79-84
21	EE	Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. ICSAMOS 2006: 115-122
20	EE	Maurizio Palesi, Shashi Kumar, Rickard Holsmark: A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS 2006: 373-384
19		Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: An Hybrid Soft Computing Approach for Automated Computer Design. STAIRS 2006: 84-95
18	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. J. UCS 12(4): 370-394 (2006)
2005
17	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Exploring Design Space of VLIW Architectures. ASAP 2005: 86-91
16	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. ASP-DAC 2005: 940-943
15	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: An evolutionary approach to network-on-chip mapping problem. Congress on Evolutionary Computation 2005: 112-119
14	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Hyperblock formation: a power/energy perspective for high performance VLIW architectures. ISCAS (4) 2005: 4090-4093
13	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 635-645 (2005)
2004
12	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: Multi-objective mapping for mesh-based NoC architectures. CODES+ISSS 2004: 182-187
11	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Multi-objective Optimization of a Parameterized VLIW Architecture. Evolvable Hardware 2004: 191-198
10	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A GA-based design space exploration framework for parameterized system-on-a-chip platforms. IEEE Trans. Evolutionary Computation 8(4): 329-346 (2004)
2003
9		Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. ESTImedia 2003: 65-72
8	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato: An evolutionary approach for reducing the switching activity in address buses. IEEE Congress on Evolutionary Computation (1) 2003: 107-114
7	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato: An evolutionary approach for reducing the energy in address buses. ISICT 2003: 76-81
6	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. PATMOS 2003: 21-30
5		Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Genetic Approach To Bus Encoding. VLSI-SOC 2003: 426-431
2002
4	EE	Maurizio Palesi, Tony Givargis: Multi-objective design space exploration using genetic algorithms. CODES 2002: 67-72
3	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Framework for Design Space Exploration of Parameterized VLSI Systems. VLSI Design 2002: 245-250
2001
2	EE	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: Parameterised system design based on genetic algorithms. CODES 2001: 177-182
1		Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. VLSI-SOC 2001: 157-168

Coauthor Index

1	Giuseppe Ascia	[1] [2] [3] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [21] [22] [24] [26] [32]
2	Vincenzo Catania	[1] [2] [3] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [21] [22] [24] [25] [26] [27] [28] [29] [30] [32] [33] [35]
3	José Duato	[34]
4	Tony Givargis	[4]
5	Rickard Holsmark	[20] [23] [25] [28] [31] [33] [35]
6	Shashi Kumar	[20] [23] [25] [28] [31] [33] [35]
7	Giuseppe Longo	[33]
8	Alessandro G. Di Nuovo	[19] [21] [24] [26] [29]
9	Juan M. Orduña	[34]
10	Antonio Parlato	[7] [8]
11	Davide Patti	[9] [11] [14] [16] [17] [19] [21] [22] [24] [26] [27] [30] [32]
12	Salvatore Signorino	[33]
13	Rafael Tornero	[34]

Colors in the list of coauthors