2003 | ||
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2 | EE | Vinod Menezes, C. B. Keshav, Sushil Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau: Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node. VLSI Design 2003: 122-127 |
2002 | ||
1 | EE | Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh: Transistor Flaring in Deep Submicron-Design Considerations. VLSI Design 2002: 299-304 |
1 | A. Amerasekera | [2] |
2 | Sushil Gupta | [2] |
3 | S. Krishnan | [2] |
4 | Vinod Menezes | [2] |
5 | G. Palau | [2] |
6 | M. Roopashree | [2] |
7 | Vipul Singhal | [1] |
8 | P. R. Suresh | [1] |
9 | K. G. Surnanth | [1] |