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Kuo-Hsing Cheng

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2008
29EEKuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-lung Lo, Wei-Bin Yang, Jiunn-Way Miaw: A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS 2008: 64-67
2007
28EEKuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su: A Sub-1V Low-Power High-Speed Static Frequency Divider. ISCAS 2007: 3848-3851
2006
27EEKuo-Hsing Cheng, Yu-lung Lo: A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. DATE Designers' Forum 2006: 178-182
26EEKuo-Hsing Cheng, Kai-Fei Chang, Yu-lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng: A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. ISCAS 2006
25EEKuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang: Self-sampled vernier delay line for built-in clock jitter measurement. ISCAS 2006
24EEKuo-Hsing Cheng, Shun-Wen Cheng: Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications. J. Inf. Sci. Eng. 22(4): 975-989 (2006)
23EEKuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee: 64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics. Journal of Circuits, Systems, and Computers 15(1): 13-28 (2006)
2005
22EEKuo-Hsing Cheng, Chen-Lung Wu, Yu-lung Lo, Chia-Wei Su: A phase-detect synchronous mirror delay for clock skew-compensation circuits. ISCAS (2) 2005: 1070-1073
21EEKuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang: A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ISCAS (2) 2005: 1174-1177
20EEKuo-Hsing Cheng, Shun-Wen Cheng: 64-Bit High-Performance Power-Aware Conditional Carry Adder Design. IEICE Transactions 88-C(6): 1322-1331 (2005)
2004
19 Kuo-Hsing Cheng, Tsung-Shen Chen, Chia Ming Tu: A 14-bit, 200 MS/s digital-to-analog converter without trimming. ISCAS (1) 2004: 353-358
18EEKuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo: A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. ISCAS (1) 2004: 777-780
17 Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang: Static divided word matching line for low-power Content Addressable Memory design. ISCAS (2) 2004: 629-632
16 Kuo-Hsing Cheng, Yu-lung Lo: A fast-lock DLL with power-on reset circuit. ISCAS (4) 2004: 357-360
15EEKuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao: 64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. ISVLSI 2004: 233-236
14EEKuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang: 64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. IWSOC 2004: 65-68
2003
13EEKuo-Hsing Cheng, Yu-lung Lo, Wen Fang Yu: A mixed-mode delay-locked loop for wide-range operation and multiphase outputs. ISCAS (2) 2003: 196-199
12EEKuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang: A new robust handshake for asymmetric asynchronous micro-pipelines. ISCAS (5) 2003: 209-212
11EEKuo-Hsing Cheng, Yung-Hsiang Lin: A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application. ISCAS (5) 2003: 425-428
10EEKuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen: BIST for clock jitter measurements. ISCAS (5) 2003: 577-580
9EEKuo-Hsing Cheng, Chung-Yu Chang, Chia-Hung Wei: A CMOS charge pump for sub-2.0 V operation. ISCAS (5) 2003: 89-92
8EEKuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu: A Robust Handshake for Asynchronous System. IWSOC 2003: 16-19
7EEKuo-Hsing Cheng, Yu-lung Lo, Wen Fang Yu, Shu-Yin Hung: A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. IWSOC 2003: 90-93
2002
6EEKuo-Hsing Cheng, Shun-Wen Cheng: Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. VLSI Design 2002: 155-159
2001
5EEKuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung: A low-power high driving ability voltage control oscillator used in PLL. ISCAS (4) 2001: 614-617
4EEShun-Wen Cheng, Kuo-Hsing Cheng: ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning. ISCAS (5) 2001: 167-170
1995
3 Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu: Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS 1995: 1572-1575
2 Chung-Yu Wu, Jr-Houng Lu, Kuo-Hsing Cheng: A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications. ISCAS 1995: 25-28
1994
1 Yuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu: Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit. ISCAS 1994: 23-26

Coauthor Index

1Chih-Hsien Chang [29]
2Chung-Yu Chang [9]
3Kai-Fei Chang [26]
4Shu-Ming Chang [21]
5Wei-Chun Chang [8] [12]
6Tsung-Shen Chen [19]
7Zong-Shen Chen [10]
8Shun-Wen Cheng [4] [6] [14] [15] [20] [23] [24]
9Yuan-Hua Chu [3]
10Chun-Fu Chung [5]
11Chan-Wei Huang [14] [25]
12Hong-Yi Huang [3]
13Cheng-Liang Hung [28] [29]
14Shu-Yin Hung [7]
15Shu-Yu Jiang [10] [17] [21] [25]
16Shu-Chang Kuo [18]
17Ching-Wen Lai [26]
18Wen-Shiuan Lee [23]
19Yang-Han Lee [12]
20Che-Yu Liao [15]
21Yung-Hsiang Lin [11]
22Yu-lung Lo [7] [13] [16] [22] [26] [27] [29]
23Jr-Houng Lu [2]
24Jiunn-Way Miaw [29]
25Chia-Wei Su [22] [28]
26Yuh-Kuang Tseng [1] [26]
27Chia Ming Tu [8] [19]
28Jinn-Shyan Wang [3]
29Chia-Hung Wei [9] [17]
30Chen-Lung Wu [22]
31Chung-Yu Wu [1] [2] [3]
32Tain-Shun Wu [3]
33Wei-Bin Yang [5] [18] [21] [29]
34Wen Fang Yu [7] [13]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)