| 2007 |
|---|
| 4 | EE | Daisuke Kosaka,
Makoto Nagata,
Yoshitaka Murasaka,
Atsushi Iwata:
Chip-Level Substrate Coupling Analysis with Reference Structures for Verification.
IEICE Transactions 90-A(12): 2651-2660 (2007) |
| 3 | EE | Daisuke Kosaka,
Makoto Nagata,
Yoshitaka Murasaka,
Atsushi Iwata:
Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits.
IEICE Transactions 90-A(2): 380-387 (2007) |
| 2002 |
|---|
| 2 | EE | Makoto Nagata,
Yoshitaka Murasaka,
Youichi Nishimori,
Takashi Morie,
Atsushi Iwata:
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models.
VLSI Design 2002: 71-76 |
| 2001 |
|---|
| 1 | EE | Yoshitaka Murasaka,
Makoto Nagata,
Takafumi Ohmoto,
Takashi Morie,
Atsushi Iwata:
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation.
ISQED 2001: 482-487 |
