| 2003 |
|---|
| 5 | EE | Manish Handa,
Rajesh Radhakrishnan,
Madhubanti Mukherjee,
Ranga Vemuri:
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs.
VLSI Design 2003: 91- |
| 2002 |
|---|
| 4 | EE | Srinivasan Dasasathyan,
Rajesh Radhakrishnan,
Ranga Vemuri:
Framework for Synthesis of Virtual Pipelines.
VLSI Design 2002: 326-331 |
| 2001 |
|---|
| 3 | EE | Rajesh Radhakrishnan,
Elena Teica,
Ranga Vemuri:
Verification of Basic Block Schedules Using RTL Transformations.
CHARME 2001: 173-178 |
| 2 | EE | Elena Teica,
Rajesh Radhakrishnan,
Ranga Vemuri:
On the verification of synthesized designs using automatically generated transformational witnesses.
DATE 2001: 798 |
| 1 | | Naren Narasimhan,
Elena Teica,
Rajesh Radhakrishnan,
Sriram Govindarajan,
Ranga Vemuri:
Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis.
Formal Methods in System Design 19(3): 237-273 (2001) |
