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Rajesh Radhakrishnan

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2003
5EEManish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri: A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs. VLSI Design 2003: 91-
2002
4EESrinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri: Framework for Synthesis of Virtual Pipelines. VLSI Design 2002: 326-331
2001
3EERajesh Radhakrishnan, Elena Teica, Ranga Vemuri: Verification of Basic Block Schedules Using RTL Transformations. CHARME 2001: 173-178
2EEElena Teica, Rajesh Radhakrishnan, Ranga Vemuri: On the verification of synthesized designs using automatically generated transformational witnesses. DATE 2001: 798
1 Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri: Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. Formal Methods in System Design 19(3): 237-273 (2001)

Coauthor Index

1Srinivasan Dasasathyan [4]
2Sriram Govindarajan [1]
3Manish Handa [5]
4Madhubanti Mukherjee [5]
5Naren Narasimhan [1]
6Elena Teica [1] [2] [3]
7Ranga Vemuri [1] [2] [3] [4] [5]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)