Samir Roy

2006
14	EE	Samir Roy, Biswajit Saha: Minority Gate Oriented Logic Design with Quantum-Dot Cellular Automata. ACRI 2006: 646-656
2005
13	EE	Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das: Synthesis of Testable Finite State Machine Through Decomposition. Asian Test Symposium 2005: 398-403
12	EE	Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das: Cellular Automata Based Test Structures with Logic Folding. VLSI Design 2005: 71-74
11	EE	Biplab K. Sikdar, Samir Roy, Debesh K. Das: A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. J. Electronic Testing 21(1): 83-93 (2005)
2004
10	EE	Chandrama Shaw, Pradipta Maji, Sourav Saha, Biplab K. Sikdar, Samir Roy, Parimal Pal Chaudhuri: Cellular Automata Based Encompression Technology for Voice Data. ACRI 2004: 258-267
2003
9	EE	Samir Roy, Biplab K. Sikdar: Power Conscious BIST Design for Sequential Circuits Using ghost-FSM. Asian Test Symposium 2003: 190-195
8	EE	Samir Roy, U. Maulik, Biplab K. Sikdar: Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines. VLSI Design 2003: 155-160
7	EE	Miklos Feher, Eugen Deretey, Samir Roy: BHB: A Simple Knowledge-Based Scoring Function to Improve the Efficiency of Database Screening. Journal of Chemical Information and Computer Sciences 43(4): 1316-1327 (2003)
2002
6	EE	Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das: Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. VLSI Design 2002: 671-676
2001
5	EE	Biplab K. Sikdar, Samir Roy, Debesh K. Das: Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. Asian Test Symposium 2001: 285-
1997
4	EE	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri: KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 257-265 (1997)
1996
3		Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri: Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach. IEEE Trans. Computers 45(4): 487-490 (1996)
1995
2	EE	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri: Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. VLSI Design 1995: 57-62
1993
1		S. Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy: Delay Fault Test Generation with Cellular Automata. VLSI Design 1993: 281-286

Coauthor Index

1	Vamsi Boppana	[1]
2	Supratik Chakraborty	[1]
3	Santanu Chattopadhyay	[2] [3] [4]
4	Parimal Pal Chaudhuri	[1] [2] [3] [4] [10]
5	Debesh Kumar Das (Debesh K. Das)	[5] [6] [11] [12] [13]
6	Sukanta Das	[12]
7	Eugen Deretey	[7]
8	Miklos Feher	[7]
9	Niloy Ganguly	[12]
10	Pradipta Maji	[10]
11	U. Maulik	[8]
12	Monalisa Mukherjee	[6]
13	S. Nandi	[1]
14	Biswajit Saha	[14]
15	Sourav Saha	[10]
16	Arijit Sarkar	[13]
17	Chandrama Shaw	[10]
18	Biplab K. Sikdar	[5] [6] [8] [9] [10] [11] [12] [13]

Colors in the list of coauthors