Jim D. Garside

2007
29	EE	A. Robinson, Jim D. Garside: Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. ACM Great Lakes Symposium on VLSI 2007: 138-143
2005
28	EE	Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou: A Low-Power Processor Architecture Optimized forWireless Devices. ASAP 2005: 185-190
27	EE	C. Brej, Jim D. Garside: A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. VLSI Design 2005: 368-373
2004
26	EE	Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury: An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC 2004: 207-215
25		Aristides Efthymiou, Jim D. Garside: A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Trans. VLSI Syst. 12(3): 325-329 (2004)
2003
24	EE	Aristides Efthymiou, Jim D. Garside: Adaptive Pipeline Structures fo Speculation Control. ASYNC 2003: 46-55
23	EE	Daranee Hormdee, Jim D. Garside, Stephen B. Furber: An asynchronous copy-back cache architecture. Microprocessors and Microsystems 27(10): 485-500 (2003)
22	EE	Luis A. Plana, P. A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu: SPA - a secure Amulet core for smartcard applications. Microprocessors and Microsystems 27(9): 431-446 (2003)
2002
21	EE	W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, P. A. Riocreux, Luis A. Plana: SPA - A Synthesisable Amulet Core for Smartcard pplications. ASYNC 2002: 201-210
20	EE	Daranee Hormdee, Jim D. Garside, Stephen B. Furber: An Asynchronous Victim Cache. DSD 2002: 4-11
19	EE	Aristides Efthymiou, Jim D. Garside: Adaptive Pipeline Depth Control for Processor Power-Management. ICCD 2002: 454-457
18	EE	Aristides Efthymiou, Jim D. Garside: An adaptive serial-parallel CAM architecture for low-power cache blocks. ISLPED 2002: 136-141
17	EE	Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside: Logic Design of Asynchronous Circuits (Tutorial Abstract). VLSI Design 2002: 26-
2001
16	EE	Daranee Hormdee, Jim D. Garside: AMULET3i Cache Architecture. ASYNC 2001: 152-161
15	EE	David W. Lloyd, Jim D. Garside: A Practical Comparison of Asynchronous Design Styles. ASYNC 2001: 36-45
14	EE	Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple: Power Management in the Amulet Microprocessors. IEEE Design & Test of Computers 18(2): 42-52 (2001)
2000
13	EE	Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, J. V. Woods, Jianwei Liu, O. Petli: AMULET3i - An Asynchronous System-on-Chip. ASYNC 2000: 162-175
12	EE	Stephen B. Furber, David A. Edwards, Jim D. Garside: AMULET3: A 100 MIPS Asynchronous Embedded Processor. ICCD 2000: 329-334
1999
11	EE	Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury: Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. ASYNC 1999: 27-35
10	EE	Jim D. Garside, Stephen B. Furber, S.-H. Chung: AMULET3 Revealed. ASYNC 1999: 51-59
9	EE	David W. Lloyd, Jim D. Garside, D. A. Gilbert: Memory Faults in Asynchronous Microprocessors. ASYNC 1999: 71-
1997
8	EE	D. A. Gilbert, Jim D. Garside: A Result Forwarding Mechanism for Asynchronous Pipelined Systems. ASYNC 1997: 2-11
7	EE	Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, P. Day, N. C. Paver: AMULET2e: An Asynchronous Embedded Controller. ASYNC 1997: 290-
6		J. V. Woods, P. Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple: AMULET1: A Asynchronous ARM Microprocessor. IEEE Trans. Computers 46(4): 385-398 (1997)
1994
5		Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods: AMULET1: A Micropipelined ARM. COMPCON 1994: 476-485
4		Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, Steve Temple, J. V. Woods: The Design and Evaluation of an Asynchronous Microprocessor. ICCD 1994: 217-220
1993
3		Jim D. Garside: A CMOS VLSI Implementation of an Asynchronous ALU. Asynchronous Design Methodologies 1993: 181-192
2		Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods: A micropipelined ARM. VLSI 1993: 211-220
1992
1		N. C. Paver, P. Day, Stephen B. Furber, Jim D. Garside, J. V. Woods: Register Locking in an Asynchronous Microprocessor. ICCD 1992: 351-355

Coauthor Index

1	W. J. Bainbridge	[13] [21] [22]
2	Andrew Bardsley	[13] [21] [22]
3	L. E. M. Brackenbury	[11] [26]
4	C. Brej	[27]
5	S.-H. Chung	[10]
6	David M. Clark	[13]
7	Jordi Cortadella	[17]
8	P. Day	[1] [2] [4] [5] [6] [7]
9	David A. Edwards	[12] [13]
10	Aristides Efthymiou	[14] [18] [19] [24] [25] [26] [28]
11	Stephen B. Furber (Steve Furber)	[1] [2] [4] [5] [6] [7] [10] [12] [13] [14] [20] [23]
12	D. A. Gilbert	[8] [9]
13	Daranee Hormdee	[16] [20] [23]
14	Mike J. G. Lewis	[11] [14]
15	Jianwei Liu	[7] [13]
16	David W. Lloyd	[9] [13] [14] [15]
17	S. Mohammadi	[13]
18	Ioannis Papaefstathiou	[28]
19	Nigel C. Paver (N. C. Paver)	[1] [2] [4] [5] [6] [7]
20	J. S. Pepper	[13]
21	O. Petli	[13]
22	Luis A. Plana	[21] [22]
23	P. A. Riocreux	[21] [22]
24	A. Robinson	[29]
25	W. Suntiamorntut	[26]
26	Steve Temple	[4] [6] [7] [13] [14] [21] [22]
27	J. V. Woods	[1] [2] [4] [5] [6] [13]
28	Alexandre Yakovlev	[17]
29	Z. C. Yu	[22]

Colors in the list of coauthors