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Debasis Samanta

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2009
15EEAshalatha Nayak, Debasis Samanta: Model-based test cases synthesis using UML interaction diagrams. ACM SIGSOFT Software Engineering Notes 34(2): 1-10 (2009)
14EEE. S. F. Najumudheen, Rajib Mall, Debasis Samanta: A dependence graph-based representation for test coverage analysis of object-oriented programs. ACM SIGSOFT Software Engineering Notes 34(2): 1-8 (2009)
2008
13EESamit Bhattacharya, Debasis Samanta, Anupam Basu: Study and modeling of user errors for virtual scanning keyboard design. CHI Extended Abstracts 2008: 3399-3404
12EEDebasish Kundu, Monalisa Sarma, Debasis Samanta: A novel approach to system testing and reliability assessment using use case model. ISEC 2008: 147-148
11EESamit Bhattacharya, Debasis Samanta, Anupam Basu: User errors on scanning keyboards: Empirical study, model and design principles. Interacting with Computers 20(3): 406-418 (2008)
2007
10EEDebasish Kundu, Debasis Samanta: A Novel Approach of Prioritizing Use Case Scenarios. APSEC 2007: 542-549
9EEDebasis Samanta, Pradipta Biswas: Designing Computer Interface for Physically Challenged Persons. ICIT 2007: 161-166
8EEDebasish Kundu, Debasis Samanta: An Approach for Assessment of Reliability of the System Using Use Case Model. ICIT 2007: 243-245
7EESomnath Dey, Debasis Samanta: Accurate Iris Boundary Detection in Iris-Based Biometric Authentication Process. PReMI 2007: 600-607
6EEDhiren M. Parmar, Monalisa Sarma, Debasis Samanta: A Novel Approach to Domino Circuit Synthesis. VLSI Design 2007: 401-406
2004
5EEDebasis Samanta, Ajit Pal: Synthesis of Low Power High Performance Dual-VT PTL Circuits. VLSI Design 2004: 85-
2003
4EEDebasis Samanta, Ajit Pal: Synthesis of Dual-VT Dynamic CMOS Circuits. VLSI Design 2003: 303-308
2002
3EEDebasis Samanta, Ajit Pal: Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. VLSI Design 2002: 193-198
2EEDebasis Samanta, Nishant Sinha, Ajit Pal: Synthesis of High Performance Low Power Dynamic CMOS Circuits. VLSI Design 2002: 99-104
2001
1EENikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal: Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. VLSI Design 2001: 227-

Coauthor Index

1Anupam Basu [11] [13]
2Samit Bhattacharya [11] [13]
3Amit M. Bhosle [1]
4Pradipta Biswas [9]
5Somnath Dey [7]
6Debasish Kundu [8] [10] [12]
7Rajib Mall [14]
8E. S. F. Najumudheen [14]
9Ashalatha Nayak [15]
10Ajit Pal [1] [2] [3] [4] [5]
11Dhiren M. Parmar [6]
12Monalisa Sarma [6] [12]
13Nishant Sinha [2]
14Nikhil Tripathi [1]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)