| 2006 |
|---|
| 7 | EE | Kuo-Hsing Cheng,
Shun-Wen Cheng:
Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications.
J. Inf. Sci. Eng. 22(4): 975-989 (2006) |
| 6 | EE | Kuo-Hsing Cheng,
Shun-Wen Cheng,
Wen-Shiuan Lee:
64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics.
Journal of Circuits, Systems, and Computers 15(1): 13-28 (2006) |
| 2005 |
|---|
| 5 | EE | Kuo-Hsing Cheng,
Shun-Wen Cheng:
64-Bit High-Performance Power-Aware Conditional Carry Adder Design.
IEICE Transactions 88-C(6): 1322-1331 (2005) |
| 2004 |
|---|
| 4 | EE | Kuo-Hsing Cheng,
Shun-Wen Cheng,
Che-Yu Liao:
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.
ISVLSI 2004: 233-236 |
| 3 | EE | Kuo-Hsing Cheng,
Shun-Wen Cheng,
Chan-Wei Huang:
64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design.
IWSOC 2004: 65-68 |
| 2002 |
|---|
| 2 | EE | Kuo-Hsing Cheng,
Shun-Wen Cheng:
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization.
VLSI Design 2002: 155-159 |
| 2001 |
|---|
| 1 | EE | Shun-Wen Cheng,
Kuo-Hsing Cheng:
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning.
ISCAS (5) 2001: 167-170 |
