| 2009 |
|---|
| 7 | EE | Nishant Chandra,
Apoorva Kumar Yati,
A. B. Bhattacharyya:
Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design.
VLSI Design 2009: 247-252 |
| 2005 |
|---|
| 6 | EE | A. B. Bhattacharyya:
Compact MOSFET Models for Low Power Analog CMOS Design.
VLSI Design 2005: 15 |
| 2002 |
|---|
| 5 | EE | A. B. Bhattacharyya,
Shrutin Ulman:
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis.
VLSI Design 2002: 207-212 |
| 1999 |
|---|
| 4 | | A. B. Bhattacharyya,
Saudas Dey:
Sub-Circuit Analysis for Power Supply Rejection Ratio in Regulated Cascode Operational Transconductance Amplifiers and Filters.
VLSI Design 1999: 164-168 |
| 1996 |
|---|
| 3 | EE | A. B. Bhattacharyya,
R. S. Rana,
S. K. Guha,
Rajendar Bahl,
R. Anand,
M. J. Zarabi,
P. A. Govindacharyulu,
U. Gupta,
V. Mohan,
Jatin Roy,
Amul Atri:
A micropower analog hearing aid on low voltage CMOS digital process.
VLSI Design 1996: 85-89 |
| 1994 |
|---|
| 2 | | A. Bandyopadhyay,
P. R. Verma,
A. B. Bhattacharyya,
M. J. Zarabi:
LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS Circuits.
VLSI Design 1994: 339-342 |
| 1990 |
|---|
| 1 | EE | Navneet K. Jain,
V. C. Prasad,
A. B. Bhattacharyya:
Delay time sensitivity in nonlinear monotone RC trees.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(5): 554-560 (1990) |
