| 2009 |
|---|
| 8 | EE | Jithendra Srinivas,
Madhusudan Rao,
Sukumar Jairam,
H. Udayakumar,
Jagdish C. Rao:
Clock gating effectiveness metrics: Applications to power optimization.
ISQED 2009: 482-487 |
| 7 | EE | R. Venkatraman,
Shrikrishna Pundoor,
Arun Koithyar,
Madhusudan Rao,
Jagdish C. Rao:
Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions.
VLSI Design 2009: 525-530 |
| 2008 |
|---|
| 6 | EE | Sukumar Jairam,
Madhusudan Rao,
Jithendra Srinivas,
Parimala Vishwanath,
H. Udayakumar,
Jagdish C. Rao:
Clock gating for power optimization in ASIC design cycle theory & practice.
ISLPED 2008: 307-308 |
| 2006 |
|---|
| 5 | EE | Bhaskar J. Karmakar,
V. Kalyana Chakravarty,
R. Venkatraman,
Jagdish C. Rao:
Enabling Quality and Schedule Predictability in SoC Design using HandoffQC.
ISQED 2006: 769-774 |
| 2002 |
|---|
| 4 | EE | Karanth Shankaranarayana,
Soujanna Sarkar,
R. Venkatraman,
Shyam S. Jagini,
N. Venkatesh,
Jagdish C. Rao,
H. Udayakumar,
M. Sambandam,
K. P. Sheshadri,
S. Talapatra,
Parag Mhatre,
Jais Abraham,
Rubin A. Parekhji:
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.
VLSI Design 2002: 781-788 |
| 2000 |
|---|
| 3 | EE | Karthikeyan Madathil,
Jagdish C. Rao,
Subash G. Chandar,
Amitabh Menon,
Avinash K. Gautam,
Amit M. Brahme,
H. Udayakumar:
A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.
VLSI Design 2000: 468- |
| 1999 |
|---|
| 2 | EE | Avinash K. Gautam,
Jagdish C. Rao,
Karthikeyan Madathil,
Vilesh Shah,
H. Udayakumar,
Amitabh Menon,
Subash G. Chandar:
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology.
ICCD 1999: 340-347 |
| 1 | EE | Avinash K. Gautam,
Jagdish C. Rao,
Rohit Rathi,
H. Udayakumar:
A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors.
VLSI Design 1999: 346-349 |
