2007 |
18 | EE | Malay K. Ganai,
Akira Mukaiyama,
Aarti Gupta,
Kazutoshi Wakabayashi:
Synthesizing "Verification Aware" Models: Why and How?
VLSI Design 2007: 50-56 |
17 | EE | Liangwei Ge,
Song Chen,
Kazutoshi Wakabayashi,
Takashi Takenaka,
Takeshi Yoshimura:
Max-Flow Scheduling in High-Level Synthesis.
IEICE Transactions 90-A(9): 1940-1948 (2007) |
2006 |
16 | EE | Takao Toi,
Noritsugu Nakamura,
Yoshinosuke Kato,
Toru Awashima,
Kazutoshi Wakabayashi,
Li Jing:
High-level synthesis challenges and solutions for a dynamically reconfigurable processor.
ICCAD 2006: 702-708 |
15 | EE | Kazutoshi Wakabayashi:
Unified Representation for Speculative Scheduling: Generalized Condition Vector.
IEICE Transactions 89-A(12): 3408-3415 (2006) |
2005 |
14 | EE | Jason Cong,
Tony Ma,
Ivo Bolsens,
Phil Moorby,
Jan M. Rabaey,
John Sanguinetti,
Kazutoshi Wakabayashi,
Yoshi Watanabe:
Are we ready for system-level synthesis?
ASP-DAC 2005 |
13 | EE | Kazutoshi Wakabayashi:
System LSI design with C-based behavioral synthesis and verification.
ISCAS (6) 2005: 5930-5933 |
2004 |
12 | EE | Kazutoshi Wakabayashi:
C-based behavioral synthesis and verification analysis on industrial design examples.
ASP-DAC 2004: 344-348 |
11 | EE | Noriaki Suzuki,
Shunsuke Kurotaki,
Masayasu Suzuki,
Naoto Kaneko,
Yutaka Yamada,
Katsuaki Deguchi,
Yohei Hasegawa,
Hideharu Amano,
Kenichiro Anjo,
Masato Motomura,
Kazutoshi Wakabayashi,
Takeo Toi,
Toru Awashima:
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
FCCM 2004: 328-329 |
2002 |
10 | EE | Aarti Gupta,
Albert E. Casavant,
Pranav Ashar,
X. G. Liu,
Akira Mukaiyama,
Kazutoshi Wakabayashi:
Property-Specific Testbench Generation for Guided Simulation.
VLSI Design 2002: 524- |
2001 |
9 | EE | Albert E. Casavant,
Aarti Gupta,
S. Liu,
Akira Mukaiyama,
Kazutoshi Wakabayashi,
Pranav Ashar:
Property-specific witness graph generation for guided simulation.
DATE 2001: 799 |
1999 |
8 | EE | Kazutoshi Wakabayashi:
C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber".
DATE 1999: 390- |
7 | EE | Sujit Dey,
Anand Raghunathan,
Niraj K. Jha,
Kazutoshi Wakabayashi:
Controller-based power management for control-flow intensive designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1496-1508 (1999) |
1997 |
6 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha,
Kazutoshi Wakabayashi:
Power Management Techniques for Control-Flow Intensive Designs.
DAC 1997: 429-434 |
1996 |
5 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha,
Kazutoshi Wakabayashi:
Controller re-specification to minimize switching activity in controller/data path circuits.
ISLPED 1996: 301-304 |
1995 |
4 | EE | Masayuki Yuguchi,
Yuichi Nakamura,
Kazutoshi Wakabayashi,
Tomoyuki Fujita:
Multi-Level Logic Minimization Based on Multi-Signal Implications.
DAC 1995: 658-662 |
3 | EE | Miodrag Potkonjak,
Sujit Dey,
Kazutoshi Wakabayashi:
Design-for-debugging of application specific designs.
ICCAD 1995: 295-301 |
1992 |
2 | EE | Kazutoshi Wakabayashi,
Hirohito Tanaka:
Global Scheduling Independent of Control Dependencies Based on Condition Vectors.
DAC 1992: 112-115 |
1985 |
1 | EE | Gotaro Odawara,
Kazuhiko Iijima,
Kazutoshi Wakabayashi:
Knowledge-based placement technique for printed wiring boards.
DAC 1985: 616-622 |