| 2007 |
|---|
| 7 | EE | Subir K. Roy:
Top Level SOC Interconnectivity Verification Using Formal Techniques.
MTV 2007: 63-70 |
| 6 | EE | Subir K. Roy,
Rubin A. Parekhji:
Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs.
VLSI Design 2007: 364-372 |
| 2002 |
|---|
| 5 | EE | Subir K. Roy,
S. Ramesh,
Supratik Chakraborty,
Tsuneo Nakata,
Sreeranga P. Rajan:
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).
VLSI Design 2002: 11-13 |
| 2000 |
|---|
| 4 | EE | Subir K. Roy,
Hiroaki Iwashita,
Tsuneo Nakata:
Formal verification based on assume and guarantee approach - a case study (short paper).
ASP-DAC 2000: 77-80 |
| 3 | EE | Subir K. Roy,
Hiroaki Iwashita,
Tsuneo Nakata:
Dataflow Analysis for Resource Contention and Register Leakage Properties.
VLSI Design 2000: 418-423 |
| 1999 |
|---|
| 2 | EE | Bupesh Pandita,
Subir K. Roy:
Design and Implementation of Viterbi Decoder Using FPGAs.
VLSI Design 1999: 611- |
| 1 | EE | Pradip K. Kar,
Subir K. Roy:
TECHMIG: A Layout Tool for Technology Migration.
VLSI Design 1999: 615-620 |
