| 2005 |
|---|
| 8 | | Shankar Balachandran,
Dinesh Bhatia:
Timing Aware Interconnect Prediction Models for FPGAs.
FPL 2005: 167-172 |
| 7 | EE | Shankar Balachandran,
Dinesh Bhatia:
A priori wirelength and interconnect estimation based on circuit characteristic.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1054-1065 (2005) |
| 2004 |
|---|
| 6 | | PariVallal Kannan,
Shankar Balachandran,
Dinesh Bhatia:
On metrics for comparing interconnect estimation methods for FPGAs.
IEEE Trans. VLSI Syst. 12(4): 381-385 (2004) |
| 2003 |
|---|
| 5 | EE | Shankar Balachandran,
Dinesh Bhatia:
A-priori wirelength and interconnect estimation based on circuit characteristics.
SLIP 2003: 77-84 |
| 2002 |
|---|
| 4 | EE | PariVallal Kannan,
Shankar Balachandran,
Dinesh Bhatia:
On metrics for comparing routability estimation methods for FPGAs.
DAC 2002: 70-75 |
| 3 | EE | PariVallal Kannan,
Shankar Balachandran,
Dinesh Bhatia:
Rapid and Reliable Routability Estimation for FPGAs.
FPL 2002: 242-252 |
| 2 | EE | Shankar Balachandran,
PariVallal Kannan,
Dinesh Bhatia:
On Routing Demand and Congestion Estimation for FPGAs.
VLSI Design 2002: 639-646 |
| 2001 |
|---|
| 1 | EE | PariVallal Kannan,
Shankar Balachandran,
Dinesh Bhatia:
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits.
FPL 2001: 37-47 |
