Takashi Morie

2008
24	EE	Daisuke Atuti, Kazuki Nakada, Takashi Morie: CMOS pulse-modulation circuit implementation of phase-locked loop neural networks. ISCAS 2008: 2174-2177
2007
23	EE	Haichao Liang, Takashi Morie, Youhei Suzuki, Kazuki Nakada, Tsutomu Miki, Hatsuo Hayashi: An FPGA-based CollisionWarning System Using Hybrid Approach. HIS 2007: 30-35
22	EE	Osamu Nomura, Takashi Morie: Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach. ICONIP (1) 2007: 1081-1090
21	EE	Shiro Dosho, Naoshi Yanagisawa, Kazuaki Sogawa, Yuji Yamada, Takashi Morie: An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter. IEICE Transactions 90-C(6): 1197-1202 (2007)
2006
20	EE	Daisuke Atuti, Takashi Morie, K. Aihara: A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms. APCCAS 2006: 1959-1963
19	EE	Kan'ya Sasaki, Takashi Morie, Atsushi Iwata: A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory. IEICE Transactions 89-C(11): 1637-1644 (2006)
18	EE	Shiro Dosho, Takashi Morie, Koji Okamoto, Yuji Yamada, Kazuaki Sogawa: A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit. IEICE Transactions 89-C(6): 739-745 (2006)
17	EE	Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. IEICE Transactions 89-C(6): 781-791 (2006)
2005
16	EE	Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. ICNC (3) 2005: 1006-1014
15	EE	Youngjae Kim, Takashi Morie: A pixel-parallel anisotropic diffusion algorithm for subjective contour generation. ISCAS (5) 2005: 4237-4240
2004
14	EE	Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. KES 2004: 995-1001
13	EE	Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. Journal of Intelligent and Fuzzy Systems 15(3-4): 173-179 (2004)
2003
12	EE	Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. KES 2003: 169-176
2002
11	EE	Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata: A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) 2002: 197-200
10	EE	Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata: Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. VLSI Design 2002: 71-76
2001
9	EE	Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata: Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC 2001: 13-14
8	EE	Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata: Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED 2001: 482-487
7	EE	Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata: An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS 2001: 1115-1122
2000
6	EE	Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata: A smart imager for the vision processing front-END. ASP-DAC 2000: 19-20
5	EE	Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata: An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC 2000: 23-24
4	EE	Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata: Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 671-678 (2000)
1999
3		Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie: A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI 1999: 77-88
1998
2		Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata: Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP 1998: 582-585
1		Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata: Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP 1998: 586-589

Coauthor Index

1	K. Aihara	[20]
2	Hiroshi Ando	[1] [12] [13]
3	Daisuke Atuti	[20] [24]
4	Shiro Dosho	[18] [21]
5	Hatsuo Hayashi	[23]
6	Hiroto Higashi	[3]
7	Mitsuru Homma	[3] [6]
8	Atsushi Iwata	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [16] [17] [19]
9	Youngjae Kim	[15]
10	Keisuke Korekado	[12] [13] [14] [17]
11	Haichao Liang	[23]
12	Masakazu Matsugu	[12] [13] [14] [16] [17]
13	Tomohiro Matsuura	[7]
14	Tsutomu Miki	[23]
15	Kenichi Murakoshi	[5]
16	Yoshitaka Murasaka	[8] [10]
17	Jin Nagai	[4] [9]
18	Makoto Nagata	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
19	Kazuki Nakada	[23] [24]
20	Hiroyuki Nakamoto	[3]
21	Teppei Nakano	[11] [12] [13] [17]
22	Youichi Nishimori	[10]
23	Osamu Nomura	[12] [13] [14] [16] [17] [22]
24	Takafumi Ohmoto	[8] [9]
25	Koji Okamoto	[18]
26	Souta Sakabayashi	[2]
27	Kan'ya Sasaki	[19]
28	Kazuaki Sogawa	[18] [21]
29	Youhei Suzuki	[23]
30	Noriaki Takeda	[3] [6]
31	Yuji Yamada	[18] [21]
32	Naoshi Yanagisawa	[21]

Colors in the list of coauthors