2008 |
36 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi,
Davide Patti:
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip.
IEEE Trans. Computers 57(6): 809-820 (2008) |
2007 |
35 | EE | Giuseppe Ascia,
Vincenzo Catania,
Alessandro G. Di Nuovo,
Maurizio Palesi,
Davide Patti:
Efficient design space exploration for application specific systems-on-a-chip.
Journal of Systems Architecture 53(10): 733-750 (2007) |
2006 |
34 | EE | Alessandro G. Di Nuovo,
Maurizio Palesi,
Davide Patti,
Giuseppe Ascia,
Vincenzo Catania:
Fuzzy decision making in embedded system design.
CODES+ISSS 2006: 223-228 |
33 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi,
Davide Patti:
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks.
ESTImedia 2006: 79-84 |
32 | EE | Giuseppe Ascia,
Vincenzo Catania,
Alessandro G. Di Nuovo,
Maurizio Palesi,
Davide Patti:
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design.
ICSAMOS 2006: 115-122 |
31 | EE | Giuseppe Ascia,
Vincenzo Catania,
Daniela Panno:
An integrated fuzzy-GA approach for buffer management.
IEEE T. Fuzzy Systems 14(4): 528-541 (2006) |
30 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi:
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip.
J. UCS 12(4): 370-394 (2006) |
2005 |
29 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi,
Davide Patti:
Exploring Design Space of VLIW Architectures.
ASAP 2005: 86-91 |
28 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi,
Davide Patti:
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems.
ASP-DAC 2005: 940-943 |
27 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi:
An evolutionary approach to network-on-chip mapping problem.
Congress on Evolutionary Computation 2005: 112-119 |
26 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi,
Davide Patti:
Hyperblock formation: a power/energy perspective for high performance VLIW architectures.
ISCAS (4) 2005: 4090-4093 |
25 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi:
A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 635-645 (2005) |
24 | EE | Giuseppe Ascia,
Vincenzo Catania,
Daniela Panno:
An evolutionary management scheme in high-performance packet switches.
IEEE/ACM Trans. Netw. 13(2): 262-275 (2005) |
2004 |
23 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi:
Multi-objective mapping for mesh-based NoC architectures.
CODES+ISSS 2004: 182-187 |
22 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi,
Davide Patti:
Multi-objective Optimization of a Parameterized VLIW Architecture.
Evolvable Hardware 2004: 191-198 |
21 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi:
A GA-based design space exploration framework for parameterized system-on-a-chip platforms.
IEEE Trans. Evolutionary Computation 8(4): 329-346 (2004) |
2003 |
20 | | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi,
Davide Patti:
EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration.
ESTImedia 2003: 65-72 |
19 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi,
Antonio Parlato:
An evolutionary approach for reducing the switching activity in address buses.
IEEE Congress on Evolutionary Computation (1) 2003: 107-114 |
18 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi,
Antonio Parlato:
An evolutionary approach for reducing the energy in address buses.
ISICT 2003: 76-81 |
17 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi:
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems.
PATMOS 2003: 21-30 |
16 | | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi:
A Genetic Approach To Bus Encoding.
VLSI-SOC 2003: 426-431 |
2002 |
15 | EE | Giuseppe Ascia,
Vincenzo Catania,
Daniela Panno:
An efficient buffer management policy based on an integrated Fuzzy-GA approach.
INFOCOM 2002 |
14 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi:
A Framework for Design Space Exploration of Parameterized VLSI Systems.
VLSI Design 2002: 245-250 |
2001 |
13 | EE | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi:
Parameterised system design based on genetic algorithms.
CODES 2001: 177-182 |
12 | | Giuseppe Ascia,
Vincenzo Catania:
A General Purpose Processor Oriented Fuzzy Reasoning.
FUZZ-IEEE 2001: 352-355 |
11 | EE | Giuseppe Ascia,
Vincenzo Catania,
Giuseppe Ficili,
Daniela Panno:
A Fuzzy Buffer Management Scheme For ATM and IP Networks.
INFOCOM 2001: 1539-1547 |
10 | EE | Giuseppe Ascia,
Vincenzo Catania,
Daniela Panno:
An adaptive fuzzy threshold scheme for high performance shared-memory switches.
SAC 2001: 456-461 |
9 | | Giuseppe Ascia,
Vincenzo Catania,
Maurizio Palesi:
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms.
VLSI-SOC 2001: 157-168 |
8 | EE | Giuseppe Ascia,
Vincenzo Catania,
Daniela Panno:
An efficient fuzzy system for traffic management in high-speed packet-switched networks.
Soft Comput. 5(4): 247-256 (2001) |
1999 |
7 | | Giuseppe Ascia,
Vincenzo Catania:
An Optimized Parallel RISC Processor for Fuzzy Computing.
Applied Informatics 1999: 454-456 |
1998 |
6 | EE | Giuseppe Ascia,
Vincenzo Catania:
A Framework for a Parallel Architecture Dedicated to Soft Computing.
VLSI Design 1998: 318-321 |
1997 |
5 | EE | Giuseppe Ascia,
Vincenzo Catania,
Giuseppe Ficili:
Design of a VLSI Hardware PET Decoder.
VLSI Design 1997: 253-256 |
1996 |
4 | | Giuseppe Ascia,
Vincenzo Catania,
Antonio Puliafito,
Lorenzo Vita:
A Reconfigurable Parallel Architecture for a Fuzzy Processor.
Inf. Sci. 88(1-4): 299-315 (1996) |
1995 |
3 | EE | Giuseppe Ascia,
Giuseppe Ficili,
Daniela Panno:
Design of a VLSI fuzzy processor for ATM traffic sources management.
LCN 1995: 62- |
2 | EE | Giuseppe Ascia,
Vincenzo Catania:
Design of a VLSI parallel processor for fuzzy computing.
VLSI Design 1995: 315-320 |
1 | | Vincenzo Catania,
Giuseppe Ascia:
A VLSI Parallel Architecture for Fuzzy Expert Systems.
IJPRAI 9(2): 421-447 (1995) |