2009 | ||
---|---|---|
68 | EE | Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: Application Specific Routing Algorithms for Networks on Chip. IEEE Trans. Parallel Distrib. Syst. 20(3): 316-330 (2009) |
2008 | ||
67 | EE | Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. NOCS 2008: 97-106 |
66 | EE | Alessandro G. Di Nuovo, Vincenzo Catania, Santo Di Nuovo, Serafino Buono: Psychology with soft computing: An integrated approach and its applications. Appl. Soft Comput. 8(1): 829-837 (2008) |
65 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Trans. Computers 57(6): 809-820 (2008) |
64 | EE | Vincenzo Catania, Maurizio Palesi, Davide Patti: Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems. TACO 5(2): (2008) |
2007 | ||
63 | EE | Alessandro G. Di Nuovo, Maurizio Palesi, Vincenzo Catania: Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems. FUZZ-IEEE 2007: 1-6 |
62 | EE | Alessandro G. Di Nuovo, Vincenzo Catania: On External Measures for Validation of Fuzzy Partitions. IFSA (1) 2007: 491-501 |
61 | EE | Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania: Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IPDPS 2007: 1-8 |
60 | EE | Vincenzo Catania, Maurizio Palesi, Davide Patti: Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario. Journal of Circuits, Systems, and Computers 16(5): 819-846 (2007) |
59 | EE | Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: Efficient design space exploration for application specific systems-on-a-chip. Journal of Systems Architecture 53(10): 733-750 (2007) |
2006 | ||
58 | EE | Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: A methodology for design of application specific deadlock-free routing algorithms for NoC systems. CODES+ISSS 2006: 142-147 |
57 | EE | Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania: Fuzzy decision making in embedded system design. CODES+ISSS 2006: 223-228 |
56 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. ESTImedia 2006: 79-84 |
55 | Alessandro G. Di Nuovo, Vincenzo Catania, Santo Di Nuovo, Serafino Buono: Evolving Fuzzy C-Means: An intelligent technique for efficient diagnosis of children mental retardation level from databases with missing values. IC-AI 2006: 290-296 | |
54 | EE | Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti: An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. ICSAMOS 2006: 115-122 |
53 | EE | Giuseppe Ascia, Vincenzo Catania, Daniela Panno: An integrated fuzzy-GA approach for buffer management. IEEE T. Fuzzy Systems 14(4): 528-541 (2006) |
52 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. J. UCS 12(4): 370-394 (2006) |
2005 | ||
51 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Exploring Design Space of VLIW Architectures. ASAP 2005: 86-91 |
50 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. ASP-DAC 2005: 940-943 |
49 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: An evolutionary approach to network-on-chip mapping problem. Congress on Evolutionary Computation 2005: 112-119 |
48 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Hyperblock formation: a power/energy perspective for high performance VLIW architectures. ISCAS (4) 2005: 4090-4093 |
47 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 635-645 (2005) |
46 | EE | Giuseppe Ascia, Vincenzo Catania, Daniela Panno: An evolutionary management scheme in high-performance packet switches. IEEE/ACM Trans. Netw. 13(2): 262-275 (2005) |
2004 | ||
45 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: Multi-objective mapping for mesh-based NoC architectures. CODES+ISSS 2004: 182-187 |
44 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: Multi-objective Optimization of a Parameterized VLIW Architecture. Evolvable Hardware 2004: 191-198 |
43 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A GA-based design space exploration framework for parameterized system-on-a-chip platforms. IEEE Trans. Evolutionary Computation 8(4): 329-346 (2004) |
2003 | ||
42 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti: EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. ESTImedia 2003: 65-72 | |
41 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato: An evolutionary approach for reducing the switching activity in address buses. IEEE Congress on Evolutionary Computation (1) 2003: 107-114 |
40 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato: An evolutionary approach for reducing the energy in address buses. ISICT 2003: 76-81 |
39 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. PATMOS 2003: 21-30 |
38 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Genetic Approach To Bus Encoding. VLSI-SOC 2003: 426-431 | |
2002 | ||
37 | EE | Giuseppe Ascia, Vincenzo Catania, Daniela Panno: An efficient buffer management policy based on an integrated Fuzzy-GA approach. INFOCOM 2002 |
36 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: A Framework for Design Space Exploration of Parameterized VLSI Systems. VLSI Design 2002: 245-250 |
2001 | ||
35 | EE | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: Parameterised system design based on genetic algorithms. CODES 2001: 177-182 |
34 | Giuseppe Ascia, Vincenzo Catania: A General Purpose Processor Oriented Fuzzy Reasoning. FUZZ-IEEE 2001: 352-355 | |
33 | EE | Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Daniela Panno: A Fuzzy Buffer Management Scheme For ATM and IP Networks. INFOCOM 2001: 1539-1547 |
32 | EE | Giuseppe Ascia, Vincenzo Catania, Daniela Panno: An adaptive fuzzy threshold scheme for high performance shared-memory switches. SAC 2001: 456-461 |
31 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. VLSI-SOC 2001: 157-168 | |
30 | Vincenzo Catania, Giuseppe Ficili, Daniela Panno: An integrated framework for traffic control in ATM networks based on soft-computing techniques. Inf. Sci. 138(1-4): 31-44 (2001) | |
29 | EE | Giuseppe Ascia, Vincenzo Catania, Daniela Panno: An efficient fuzzy system for traffic management in high-speed packet-switched networks. Soft Comput. 5(4): 247-256 (2001) |
1999 | ||
28 | Vincenzo Catania, Giuseppe Ficili, Daniela Panno: A Framework for Traffic Control in Integrated Services Networks Based on Fuzzy Logic. Applied Informatics 1999: 427-429 | |
27 | Giuseppe Ascia, Vincenzo Catania: An Optimized Parallel RISC Processor for Fuzzy Computing. Applied Informatics 1999: 454-456 | |
26 | EE | Vincenzo Catania, Giuseppe Ficili, Daniela Panno: On the impact of traffic control algorithms on resource management in ATM networks. Computer Communications 22(3): 258-265 (1999) |
1998 | ||
25 | EE | Giuseppe Ascia, Vincenzo Catania: A Framework for a Parallel Architecture Dedicated to Soft Computing. VLSI Design 1998: 318-321 |
1997 | ||
24 | EE | Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili: Design of a VLSI Hardware PET Decoder. VLSI Design 1997: 253-256 |
1996 | ||
23 | EE | Vincenzo Catania, Antonio Puliafito, Salvatore Riccobene, Lorenzo Vita: Monitoring performance in distributed systems. Computer Communications 19(9-10): 788-803 (1996) |
22 | EE | Vincenzo Catania, Giuseppe Ficili, Sergio Palazzo, Daniela Panno: A comparative analysis of fuzzy versus conventional policing mechanisms for ATM networks. IEEE/ACM Trans. Netw. 4(3): 449-459 (1996) |
21 | Giuseppe Ascia, Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: A Reconfigurable Parallel Architecture for a Fuzzy Processor. Inf. Sci. 88(1-4): 299-315 (1996) | |
20 | Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: A Fuzzy Approach to Mapping Problems. Inf. Sci. 95(3): 191-217 (1996) | |
1995 | ||
19 | EE | Vincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo: A soft computing approach to hardware software codesign. Great Lakes Symposium on VLSI 1995: 158-163 |
18 | EE | Vincenzo Catania, Giuseppe Ficili, Sergio Palazzo, Daniela Panno: A fuzzy decision maker for source traffic control in high speed networks. ICNP 1995: 136-143 |
17 | EE | Vincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo: A Framework for Codesign Based on Fuzzy Logic and Genetic Algorithms. IEA/AIE 1995: 797-804 |
16 | EE | Vincenzo Catania, Marco Russo: Analog gates for a VLSI fuzzy processor. VLSI Design 1995: 299-304 |
15 | EE | Giuseppe Ascia, Vincenzo Catania: Design of a VLSI parallel processor for fuzzy computing. VLSI Design 1995: 315-320 |
14 | Vincenzo Catania, Antonio Puliafito, Salvatore Riccobene, Lorenzo Vita: Design and Performance Analysis of a Disk Array System. IEEE Trans. Computers 44(10): 1236-1247 (1995) | |
13 | Vincenzo Catania, Giuseppe Ascia: A VLSI Parallel Architecture for Fuzzy Expert Systems. IJPRAI 9(2): 421-447 (1995) | |
1994 | ||
12 | Vincenzo Catania, Antonio Puliafito, Salvatore Riccobene, Lorenzo Vita: Performance Evaluation of a Partial Dynamic Declustering Disk Array System. HPDC 1994: 244-252 | |
11 | Vincenzo Catania, O. Granato, Antonio Puliafito, Lorenzo Vita: PMT: A Tool to Monitor Performances in Distributed Systems. HPDC 1994: 279-286 | |
10 | EE | Salvatore Casale, Vincenzo Catania, Aurelio La Corte: Service integration issues on an ATM DQDB MAN. Computer Communications 17(6): 407-418 (1994) |
1993 | ||
9 | Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: A Model for Performance Evaluation of Gracefully Degrading Systems. Comput. J. 36(2): 177-185 (1993) | |
8 | EE | Salvatore Casale, Vincenzo Catania, Aurelio La Corte, Lorenzo Vita: Service management on an ATM DQDB MAN. Computer Communications 16(3): 147-154 (1993) |
7 | EE | Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: High-speed data service in distributed systems based on SMDS. Computer Communications 16(7): 394-402 (1993) |
1991 | ||
6 | EE | Vincenzo Catania, L. Mazzola, Antonio Puliafito, Lorenzo Vita: Performance analysis of DQDB behaviour with priority levels. ICDCS 1991: 44-51 |
5 | Vincenzo Catania, Mario Gerla, Claudio Pavanelli: A Routing Strategy for MAN Interconnection. INFOCOM 1991: 608-615 | |
4 | EE | Vincenzo Catania, Salvatore Cavalieri, Lorenzo Vita: Rearrangeable switch fabric for fast packet switching. Computer Communications 14(8): 451-460 (1991) |
1990 | ||
3 | Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: Availability and Performability Assessment in LAN Interconnection. INFOCOM 1990: 1181-1187 | |
1989 | ||
2 | Salvatore Casale, Vincenzo Catania, Antonio Puliafito, Lorenzo Vita: A Multiple Spanning Tree Protocol in Bridged LANs. IFIP Congress 1989: 633-638 | |
1 | EE | Salvatore Casale, Vincenzo Catania, Alberto Faro, Nikolai Parchenkov, Lorenzo Vita: Design and performance evaluation of an optical fibre LAN with double token rings. Computer Communications 12(3): 158-166 (1989) |