2008 |
32 | EE | Zhen Zhang,
Alain Greiner,
Sami Taktak:
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip.
DAC 2008: 441-446 |
31 | EE | Ivan Miro Panades,
Fabien Clermidy,
Pascal Vivet,
Alain Greiner:
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture.
NOCS 2008: 139-148 |
30 | EE | Abbas Sheibanyrad,
Alain Greiner:
Two efficient synchronous <--> asynchronous converters well-suited for networks-on-chip in GALS architectures.
Integration 41(1): 17-26 (2008) |
2007 |
29 | EE | Abbas Sheibanyrad,
Ivan Miro Panades,
Alain Greiner:
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture.
DATE 2007: 1090-1095 |
28 | | Abbas Sheibanyrad,
Alain Greiner:
Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures.
ESA 2007: 27-33 |
27 | EE | Ivan Miro Panades,
Alain Greiner:
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures.
NOCS 2007: 83-94 |
26 | EE | Matthieu Tuna,
Mounir Benabdenbi,
Alain Greiner:
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester.
VTS 2007: 447-454 |
25 | EE | Hervé Charlery,
Adrijean Andriahantenaina,
Alain Greiner:
Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN.
Computers & Electrical Engineering 33(4): 299-309 (2007) |
2006 |
24 | EE | Rabie Ben Atitallah,
Smaïl Niar,
Alain Greiner,
Samy Meftali,
Jean-Luc Dekeyser:
Estimating Energy Consumption for an MPSoC Architectural Exploration.
ARCS 2006: 298-310 |
23 | EE | Emmanuel Viaud,
François Pêcheux,
Alain Greiner:
An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles.
DATE 2006: 94-99 |
22 | EE | Frédéric Pétrot,
Alain Greiner,
Pascal Gomez:
On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures.
DSD 2006: 53-60 |
21 | EE | Abbas Sheibanyrad,
Alain Greiner:
Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures.
PATMOS 2006: 191-202 |
20 | | Etienne Faure,
Alain Greiner,
Daniela Genius:
A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications.
ReCoSoC 2006: 237-242 |
19 | | Alain Greiner,
Frédéric Pétrot,
M. Carrier,
Mounir Benabdenbi,
Roselyne Chotin-Avot,
Raphaël Labayrade:
MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation.
ReCoSoC 2006: 24-30 |
2004 |
18 | EE | Mounir Benabdenbi,
Alain Greiner,
François Pêcheux,
Emmanuel Viaud,
Matthieu Tuna:
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores.
DATE 2004: 712-713 |
17 | EE | Marie-Minerve Louërat,
Tuong P. Nguyen,
Vincent Bourguet,
L. de Lamarre,
Alain Greiner:
A language to desing generators of analog functions (poster).
FDL 2004: 30-32 |
2003 |
16 | EE | Adrijean Andriahantenaina,
Alain Greiner:
Micro-Network for SoC: Implementation of a 32-Port SPIN network.
DATE 2003: 11128-11129 |
15 | EE | Adrijean Andriahantenaina,
Hervé Charlery,
Alain Greiner,
Laurent Mortiez,
Cesar Albenes Zeferino:
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network.
DATE 2003: 20070-20073 |
2001 |
14 | EE | Mohamed Dessouky,
Andreas Kaiser,
Marie-Minerve Louërat,
Alain Greiner:
Analog design for reuse - case study: very low-voltage sigma-delta modulator.
DATE 2001: 353-360 |
13 | | Jean Lou Desbarbieux,
Olivier Glück,
Amal Zerrouki,
Alexandre Fenyo,
Alain Greiner,
Franck Wajsbürt,
Cyril Spasevski,
Fabrício Silva,
E. Dreyfus:
Protocol and Performance Analysis of the MPC Parallel Computer.
IPDPS 2001: 52 |
2000 |
12 | EE | Pierre Guerrier,
Alain Greiner:
A Generic Architecture for On-Chip Packet-Switched Interconnections.
DATE 2000: 250-256 |
1997 |
11 | EE | Frédéric Pétrot,
Denis Hommais,
Alain Greiner:
A Simulation Environment for Core Based Embedded Systems.
Annual Simulation Symposium 1997: 86-91 |
10 | EE | Frédéric Pétrot,
Denis Hommais,
Alain Greiner:
Cycle precise core based hardware/software system simulation with predictable event propagation.
EUROMICRO 1997: 182-187 |
1995 |
9 | | Marcello Duhalde,
Alain Greiner,
Frédéric Pétrot:
A High Performance Modular Embedded ROM Architecture.
ISCAS 1995: 1057-1060 |
1994 |
8 | | M. Hirech,
O. Florent,
Alain Greiner,
E. Rejouan:
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking.
EDAC-ETC-EUROASIC 1994: 668 |
7 | | Luc Burgun,
N. Dictus,
Alain Greiner,
E. Pradho,
C. Sarwary:
Multilevel Logic Synthesis of Very High Complexity Circuits.
EDAC-ETC-EUROASIC 1994: 669 |
6 | | Alain Greiner,
L. Lucas,
Franck Wajsbürt,
Laurent Winckel:
Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library.
EDAC-ETC-EUROASIC 1994: 9-13 |
5 | EE | Luc Burgun,
N. Dictus,
Alain Greiner,
E. Prado Lopes,
C. Sarwary:
Multilevel logic optimization of very high complexity circuits.
EURO-DAC 1994: 14-19 |
4 | EE | Alain Greiner,
Frédéric Pétrot:
Using C to write portable CMOS VLSI module generators.
EURO-DAC 1994: 676-681 |
3 | | Denis Archambaud,
Pascal Faudemay,
Alain Greiner:
RAPID-2, An Object-Oriented Associative Memory Applicable to Genome Data Processing.
HICSS (5) 1994: 150-159 |
2 | | M. Hirech,
O. Florent,
Alain Greiner,
E. Rejouan:
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking.
ISCAS 1994: 89-92 |
1992 |
1 | | Lotfi Ben Ammar,
Alain Greiner:
FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout.
Synthesis for Control Dominated Circuits 1992: 133-151 |