| 2007 | 
| 30 | EE | Mark B. Josephs:
Gate-level modelling and verification of asynchronous circuits using CSPM and FDR.
ASYNC 2007: 83-94 | 
| 29 | EE | Mark B. Josephs,
Hemangee K. Kapoor:
Controllable Delay-Insensitive Processes.
Fundam. Inform. 78(1): 101-130 (2007) | 
| 2006 | 
| 28 | EE | Jun Xu,
Reza Sotudeh,
Mark B. Josephs:
Asynchronous Packet-Switching for Networks-on-Chip.
ACSD 2006: 201-207 | 
| 27 | EE | Hemangee K. Kapoor,
Mark B. Josephs,
Dennis P. Furey:
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments.
Fundam. Inform. 70(1-2): 21-48 (2006) | 
| 2005 | 
| 26 | EE | Hemangee K. Kapoor,
Mark B. Josephs:
Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation.
ACSD 2005: 58-67 | 
| 2004 | 
| 25 | EE | Mark B. Josephs:
Models for Data-Flow Sequential Processes.
25 Years Communicating Sequential Processes 2004: 85-97 | 
| 24 | EE | Hemangee K. Kapoor,
Mark B. Josephs,
Dennis P. Furey:
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments.
ACSD 2004: 89-98 | 
| 23 | EE | Hemangee K. Kapoor,
Mark B. Josephs:
Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis.
DAC 2004: 830-833 | 
| 22 | EE | Hemangee K. Kapoor,
Mark B. Josephs:
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench.
Inf. Process. Lett. 89(6): 293-296 (2004) | 
| 2003 | 
| 21 | EE | Mark B. Josephs:
An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits.
ASYNC 2003: 121-131 | 
| 2002 | 
| 20 | EE | Mark B. Josephs,
Dennis P. Furey:
A Programming Approach to the Design of Asynchronous Logic Blocks.
Concurrency and Hardware Design 2002: 34-60 | 
| 19 | EE | Igor Lemberski,
Mark B. Josephs:
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions.
PATMOS 2002: 92-100 | 
| 2000 | 
| 18 | EE | Mark B. Josephs,
Dennis P. Furey:
Delay-Insensitive Interface Specification and Synthesis.
DATE 2000: 169- | 
| 1998 | 
| 17 | EE | Mark B. Josephs:
Formal Derivation of a Loadable Asynchronous Counter.
MPC 1998: 234-253 | 
| 16 |   | Mark B. Josephs:
Protocol Specification, Testing and Verification XV, by Piotr Dembinski and Marek Sredniawa (Editors), Chapman and Hall, 1996 (Book Review).
Softw. Test., Verif. Reliab. 8(1): 49 (1998) | 
| 1997 | 
| 15 |   | Mark B. Josephs,
Andrew M. Bailey:
The Use of SI-Algebra in the Design of Sequencer Circuits.
Formal Asp. Comput. 9(4): 395-408 (1997) | 
| 1996 | 
| 14 | EE | Mark B. Josephs,
Jelio T. Yantchev:
CMOS design of the tree arbiter element.
IEEE Trans. VLSI Syst. 4(4): 472-476 (1996) | 
| 1995 | 
| 13 | EE | Jelio T. Yantchev,
C. G. Huang,
Mark B. Josephs,
I. M. Nedelchev:
Low-latency asynchronous FIFO buffers.
ASYNC 1995: 24-31 | 
| 12 | EE | Andrew M. Bailey,
Mark B. Josephs:
Sequencer circuits for VLSI programming.
ASYNC 1995: 82-90 | 
| 1994 | 
| 11 |   | Iain S. C. Houston,
Mark B. Josephs:
Specifying Distributed CICS in Z: Accessing Local and Remote Resources (Short Communication).
Formal Asp. Comput. 6(5): 569-579 (1994) | 
| 1993 | 
| 10 |   | Mark B. Josephs,
Jan Tijmen Udding:
Implementing a Stack as a Delay-insensitive Circuit.
Asynchronous Design Methodologies 1993: 123-135 | 
| 9 |   | Rix Groenboom,
Mark B. Josephs,
Paul G. Lucassen,
Jan Tijmen Udding:
Normal Form in a Delay-Insensitive Algebra.
Asynchronous Design Methodologies 1993: 57-70 | 
| 1992 | 
| 8 |   | Mark B. Josephs,
Rudolf H. Mak,
Jan Tijmen Udding,
Tom Verhoeff,
Jelio T. Yantchev:
High-Level Design of an Asynchronous Packet-Routing Chip.
Designing Correct Circuits 1992: 261-274 | 
| 7 |   | Mark B. Josephs:
Receptive Process Theory.
Acta Inf. 29(1): 17-31 (1992) | 
| 1990 | 
| 6 |   | Mark B. Josephs,
Jan Tijmen Udding:
An Algebra for Delay-Insensitive Circuits.
CAV 1990: 343-352 | 
| 5 |   | Mark B. Josephs,
Jan Tijmen Udding:
Delay-Insensitive Circuits: An Algebraic Approach to their Design.
CONCUR 1990: 342-366 | 
| 1989 | 
| 4 |   | Mark B. Josephs:
The Semantics of Lazy Functional Languages.
Theor. Comput. Sci. 68(1): 105-111 (1989) | 
| 1988 | 
| 3 |   | Mark B. Josephs:
A State-Based Approach to Communicating Processes.
Distributed Computing 3(1): 9-18 (1988) | 
| 2 |   | Mark B. Josephs:
The Data Refinement Calculator for Z Specifications.
Inf. Process. Lett. 27(1): 29-33 (1988) | 
| 1986 | 
| 1 |   | Mark B. Josephs:
Functional Programming with Side-Effects.
Sci. Comput. Program. 7(3): 279-296 (1986) |