| 2002 |
|---|
| 8 | EE | G. N. Hoyer,
Gin Yee,
Carl Sechen:
Locally clocked pipelines and dynamic logic.
IEEE Trans. VLSI Syst. 10(1): 58-62 (2002) |
| 2000 |
|---|
| 7 | EE | Jovanka Ciric,
Gin Yee,
Carl Sechen:
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic.
DATE 2000: 277-282 |
| 6 | EE | Larry McMurchie,
Su Kio,
Gin Yee,
Tyler Thorp,
Carl Sechen:
Output Prediction Logic: A High-Performance CMOS Design Technique.
ICCD 2000: 247- |
| 5 | EE | Gin Yee,
Tyler Thorp,
Ron Christopherson,
Ban P. Wang,
Carl Sechen:
An Automated Shielding Algorithm and Tool For Dynamic Circuits.
ISQED 2000: 369-374 |
| 4 | EE | Gin Yee,
Carl Sechen:
Clock-delayed domino for dynamic circuit design.
IEEE Trans. VLSI Syst. 8(4): 425-430 (2000) |
| 1999 |
|---|
| 3 | EE | Tyler Thorp,
Gin Yee,
Carl Sechen:
Design and Synthesis of Monotonic Circuits.
ICCD 1999: 569-572 |
| 1998 |
|---|
| 2 | EE | Tyler Thorp,
Gin Yee,
Carl Sechen:
Domino logic synthesis using complex static gates.
ICCAD 1998: 242-247 |
| 1996 |
|---|
| 1 | EE | Gin Yee,
Carl Sechen:
Clock-Delayed Domino for Adder and Combinational Logic Desig.
ICCD 1996: 332- |
