| 2004 |
|---|
| 9 | EE | Hassan Al Atat,
Iyad Ouaiss:
Register Binding for FPGAs with Embedded Memory.
FCCM 2004: 167-175 |
| 8 | EE | Dalia Dagher,
Iyad Ouaiss:
Storage Allocation for Diverse FPGA Memory Specifications.
FPL 2004: 606-616 |
| 2001 |
|---|
| 7 | EE | Iyad Ouaiss,
Ranga Vemuri:
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers.
DATE 2001: 650-657 |
| 6 | EE | Amit Kasat,
Iyad Ouaiss,
Ranga Vemuri:
Memory Synthesis for FPGA-Based Reconfigurable Computers.
FPL 2001: 70-80 |
| 5 | | Iyad Ouaiss,
Ranga Vemuri:
Global memory mapping for FPGA-based reconfigurable systems.
IPDPS 2001: 144 |
| 2000 |
|---|
| 4 | EE | Iyad Ouaiss,
Ranga Vemuri:
Efficient Resource Arbitration in Reconfigurable Computing Environments.
DATE 2000: 560-566 |
| 1999 |
|---|
| 3 | EE | Meenakshi Kaul,
Ranga Vemuri,
Sriram Govindarajan,
Iyad Ouaiss:
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications.
DAC 1999: 616-622 |
| 1998 |
|---|
| 2 | EE | Sriram Govindarajan,
Iyad Ouaiss,
Meenakshi Kaul,
Vinoo Srinivasan,
Ranga Vemuri:
An Effective Design System for Dynamically Reconfigurable Architectures.
FCCM 1998: 312-313 |
| 1 | | Iyad Ouaiss,
Sriram Govindarajan,
Vinoo Srinivasan,
Meenakshi Kaul,
Ranga Vemuri:
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures.
IPPS/SPDP Workshops 1998: 31-36 |
