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Antonio J. Acosta

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2007
20EERenato Rimolo-Donadio, Antonio J. Acosta, Wolfgang H. Krautschneider: Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications. ISCAS 2007: 1799-1802
19EEJavier Castro, Pilar Parra, Manuel Valencia, Antonio J. Acosta: Asymmetric clock driver for improved power and noise performances. ISCAS 2007: 893-896
2006
18EERaúl Jiménez, Pilar Parra, Javier Castro, Manuel Sánchez, Antonio J. Acosta: Optimization of Master-Slave Flip-Flops for High-Performance Applications. PATMOS 2006: 439-449
2005
17EEPilar Parra, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia: Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electronics 1(1): 11-19 (2005)
2003
16EERaúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta: A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. PATMOS 2003: 491-500
2002
15 Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002 Springer 2002
14EERaúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta: A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. PATMOS 2002: 209-218
13EEPilar Parra, Antonio J. Acosta, Manuel Valencia: Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS 2002: 448-457
2001
12EEPaulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia: HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE 2001: 467-471
11EENatividad Martínez Madrid, Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda: Analog/mixed-signal IP modeling for design reuse. DATE 2001: 766-767
10EEManuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia: Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) 2001: 483-486
2000
9EEEduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas: A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. DATE 2000: 534-538
8EEJorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia: Degradation Delay Model Extension to CMOS Gates. PATMOS 2000: 149-158
7EERaúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda: An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. PATMOS 2000: 295-305
6EEAntonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia: Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS 2000: 316-326
1999
5EET. A. García, Antonio J. Acosta, J. M. Mora, J. Ramos, José Luis Huertas: Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. J. Electronic Testing 15(1-2): 115-127 (1999)
1998
4EET. A. García, Antonio J. Acosta, José L. Huertas, J. M. Mora, J. Ramos: Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. VTS 1998: 92-97
1995
3EEAntonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barrios, Raúl Jiménez, José L. Huertas: New CMOS VLSI linear self-timed architectures. ASYNC 1995: 14-23
2 Manuel Valencia, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano: Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers 44(12): 1456-1461 (1995)
1993
1 Manuel J. Bellido, Manuel Valencia, Antonio J. Acosta, Angel Barriga Barrios, José Luis Huertas, Rafael Domínguez-Castro: A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS 1993: 2019-2022

Coauthor Index

1Angel Barriga Barrios [1] [3]
2Javier Castro [18] [19]
3Manuel Jesús Bellido Díaz (Manuel J. Bellido) [1] [2] [3] [6] [8] [10] [12] [15]
4Rafael Domínguez-Castro [1]
5T. A. García [4] [5]
6Bertrand Hochet [15]
7José Luis Huertas (José L. Huertas) [1] [2] [3] [4] [5] [9]
8Raúl Jiménez [3] [6] [7] [14] [16] [17] [18]
9Jorge Juan-Chico [6] [8] [10] [12]
10Wolfgang H. Krautschneider [20]
11Natividad Martínez Madrid [11]
12J. M. Mora [4] [5]
13Pilar Parra [13] [14] [16] [17] [18] [19]
14Eduardo J. Peralías [7] [9] [11]
15J. Ramos [4] [5]
16Renato Rimolo-Donadio [20]
17Adoración Rueda [7] [9] [11]
18Paulino Ruiz-de-Clavijo [8] [10] [12]
19Manuel Sánchez [18]
20Santiago Sánchez-Solano [2]
21Pedro Sanmartín [14] [16]
22Manuel Valencia [1] [2] [3] [6] [8] [10] [12] [13] [17] [19]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)