| 2007 |
|---|
| 38 | EE | Hosna Jabbari,
Jon C. Muzio,
Lin Sun:
A New Class of Cellular Automata.
DSD 2007: 331-338 |
| 2005 |
|---|
| 37 | EE | Jacqueline E. Rice,
Jon C. Muzio:
A Characterization of Antisymmetry in Boolean and Multi-Valued Functions.
ISMVL 2005: 270-275 |
| 2004 |
|---|
| 36 | | Jing Zhong,
Jon C. Muzio:
An Investigation of Non-Linear Machines as PRPGs in BIST.
ESA/VLSI 2004: 360-366 |
| 35 | EE | Laurence Tianruo Yang,
Jon C. Muzio:
Testing Methodologies for Embedded Systems and Systems-on-Chip.
ICESS 2004: 15-24 |
| 2002 |
|---|
| 34 | EE | Laurence Tianruo Yang,
Jon C. Muzio:
Redundant transformations for BIST testability metrics-based data path allocation.
APCCAS (2) 2002: 119-123 |
| 33 | EE | Jacqueline E. Rice,
Jon C. Muzio:
Use of the Autocorrelation Function in the Classification of Switching Functions.
DSD 2002: 244-251 |
| 32 | EE | Micaela Serra,
Jon C. Muzio:
The IT Support for Acquired Brain Injury Patients - the Design and Evaluation of a New Software Package.
HICSS 2002: 135 |
| 31 | EE | Jacqueline E. Rice,
Jon C. Muzio:
Antisymmetries in the realization of Boolean functions.
ISCAS (4) 2002: 69-72 |
| 2000 |
|---|
| 30 | EE | Elena Dubrova,
Peeter Ellervee,
D. Michael Miller,
Jon C. Muzio:
TOP: An Algorithm for Three-Level Optimization of PLDs.
DATE 2000: 751 |
| 29 | EE | Elena Dubrova,
Jon C. Muzio:
Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits.
IEEE Trans. Computers 49(11): 1285-1289 (2000) |
| 1999 |
|---|
| 28 | EE | Micaela Serra,
E. Wang,
Jon C. Muzio:
A Multimedia Virtual Lab for Digital Logic Design.
MSE 1999: 39-40 |
| 27 | | Kevin Cattell,
Shujian Zhang,
Micaela Serra,
Jon C. Muzio:
2-by-n Hybrid Cellular Automata with Regular Configuration: Theory and Application.
IEEE Trans. Computers 48(3): 285-295 (1999) |
| 1997 |
|---|
| 26 | EE | Elena Dubrova,
Jon C. Muzio,
Bernhard von Stengel:
Finding Composition Trees for Multiple-Valued Functions.
ISMVL 1997: 19-26 |
| 25 | EE | Kevin Cattell,
Jon C. Muzio:
Partial Symmetry in Cellular Automata Rule Vectors.
J. Electronic Testing 11(2): 187-190 (1997) |
| 1996 |
|---|
| 24 | EE | Elena Dubrova,
Jon C. Muzio:
Testability of Generalized Multiple-Valued Reed-Muller Circuits.
ISMVL 1996: 56-61 |
| 23 | | Kevin Cattell,
Jon C. Muzio:
Analysis of One-Dimensional Linear Hybrid Cellular Automata over GF(q).
IEEE Trans. Computers 45(7): 782-792 (1996) |
| 22 | EE | Shujian Zhang,
D. Michael Miller,
Jon C. Muzio:
Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping".
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1588-1590 (1996) |
| 21 | EE | Kevin Cattell,
Jon C. Muzio:
Synthesis of one-dimensional linear hybrid cellular automata.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(3): 325-335 (1996) |
| 20 | EE | David Wessels,
Jon C. Muzio:
The dangers of simplistic delay models.
J. Electronic Testing 8(1): 61-69 (1996) |
| 1995 |
|---|
| 19 | EE | Elena Dubrova,
Dilian Gurov,
Jon C. Muzio:
The Evaluation of Full Sensitivity for Test Generation in MVL Circuits.
ISMVL 1995: 104- |
| 18 | EE | Shujian Zhang,
Jon C. Muzio:
Evaluating the safety of self-checking circuits.
J. Electronic Testing 6(2): 243-253 (1995) |
| 17 | EE | Shujian Zhang,
Rod Byrne,
Jon C. Muzio,
D. Michael Miller:
Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults.
J. Electronic Testing 7(3): 209-221 (1995) |
| 1994 |
|---|
| 16 | | Shujian Zhang,
Rod Byrne,
Jon C. Muzio,
D. Michael Miller:
Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults.
ISCAS 1994: 69-72 |
| 15 | | Elena Dubrova,
Dilian Gurov,
Jon C. Muzio:
Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits.
ISMVL 1994: 284-288 |
| 1993 |
|---|
| 14 | | David Wessels,
Jon C. Muzio:
Probabilistic Identification of Critical Components for Circuit Delays.
DFT 1993: 215-222 |
| 13 | EE | Chao Feng,
Jon C. Muzio,
Fabrizio Lombardi:
On the testability of array structures for FFT computation.
J. Electronic Testing 4(3): 215-224 (1993) |
| 1992 |
|---|
| 12 | | David Wessels,
Jon C. Muzio:
Concurrent Checking and Unidirectional Errors in Multiple-Valued Circuits.
ISMVL 1992: 166-173 |
| 11 | | P. K. Lui,
Jon C. Muzio:
Boolean Matrix Transforms for the Minimization of Modulo-2 Canonical Expansions.
IEEE Trans. Computers 41(3): 342-348 (1992) |
| 1991 |
|---|
| 10 | EE | P. K. Lui,
Jon C. Muzio:
Constrained parity testing.
J. Electronic Testing 2(3): 279-291 (1991) |
| 1990 |
|---|
| 9 | | Jon C. Muzio:
Concerning the Maximum Size of the Terms in the Realization of Symmetric Functions.
ISMVL 1990: 292-299 |
| 8 | EE | Fabrizio Lombardi,
Yinan N. Shen,
Jon C. Muzio:
On the testability of array structures for FFT computation.
SPDP 1990: 519-522 |
| 7 | EE | Micaela Serra,
Terry Slater,
Jon C. Muzio,
D. Michael Miller:
The analysis of one-dimensional linear cellular automata and their aliasing properties.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 767-778 (1990) |
| 1988 |
|---|
| 6 | EE | Micaela Serra,
Jon C. Muzio:
Space compaction for multiple-output circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1105-1113 (1988) |
| 1987 |
|---|
| 5 | | Micaela Serra,
Jon C. Muzio:
Testing Programmable Logic Arrays by Sum of Syndromes.
IEEE Trans. Computers 36(9): 1097-1101 (1987) |
| 1984 |
|---|
| 4 | | D. Michael Miller,
Jon C. Muzio:
Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks.
IEEE Trans. Computers 33(8): 765-769 (1984) |
| 1983 |
|---|
| 3 | | D. Michael Miller,
Jon C. Muzio:
Spectral Fault Signatures for Internally Unate Combinational Networks.
IEEE Trans. Computers 32(11): 1058-1062 (1983) |
| 1980 |
|---|
| 2 | | Jon C. Muzio:
Composite Spectra and the Analysis of Switching Circuits.
IEEE Trans. Computers 29(8): 750-753 (1980) |
| 1977 |
|---|
| 1 | | J. A. Bate,
Jon C. Muzio:
Three Cell Structures for Ternary Cellular Arrays.
IEEE Trans. Computers 26(12): 1191-1202 (1977) |
