Maurizio Zamboni

2009
23	EE	Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni: A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design. Integration 42(1): 47-60 (2009)
2007
22	EE	Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni: An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. DATE 2007: 1424-1429
2004
21		Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. VLSI Syst. 12(4): 349-358 (2004)
20	EE	Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectronics Journal 35(10): 849-857 (2004)
2003
19	EE	Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni: Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. FPGA 2003: 246
18	EE	M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS 2003: 121-130
17	EE	Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni: Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS 2003: 90-100
16	EE	Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Coupled electro-thermal modeling and optimization of clock networks. Microelectronics Journal 34(12): 1175-1185 (2003)
15	EE	Maurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. VLSI Signal Processing 35(2): 137-153 (2003)
2002
14	EE	Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni: Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. FPL 2002: 332-339
13	EE	Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni: Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS 2002: 198-208
12	EE	Guido Masera, M. Mazza, Gianluca Piccinini, F. Viglione, Maurizio Zamboni: Architectural strategies for low-power VLSI turbo decoders. IEEE Trans. VLSI Syst. 10(3): 279-285 (2002)
2001
11	EE	Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni: Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED 2001: 287-290
10	EE	Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Hierarchical power supply noise evaluation for early power grid design prediction. SLIP 2001: 183-188
9	EE	Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Switching Noise Analysis Framework For High Speed Logic Families. VLSI Design 2001: 524-530
2000
8	EE	F. Viglione, Guido Masera, Gianluca Piccinini, M. Ruo Roch, Maurizio Zamboni: A 50 Mbit/s Iterative Turbo-Decoder. DATE 2000: 176-180
7	EE	Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Noise Safety Design Methodologies. ISQED 2000: 157-
6	EE	Mariagrazia Graziano, Marco Delaurenti, Maurizio Zamboni: Power supply design parameters prediction for high performance IC design flows. SLIP 2000: 61-67
1999
5		Guido Masera, Gianluca Piccinini, M. Ruo Roch, Maurizio Zamboni: A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. Applied Informatics 1999: 51-54
4	EE	Guido Masera, Gianluca Piccinini, Massimo Ruo Roth, Maurizio Zamboni: New 2 Gbit/s CMOS I/O pads. Great Lakes Symposium on VLSI 1999: 82-85
3	EE	Guido Masera, Gianluca Piccinini, M. Ruo Roch, Maurizio Zamboni: VLSI architectures for turbo codes. IEEE Trans. VLSI Syst. 7(3): 369-379 (1999)
1998
2	EE	Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni: Fanout optimization under a submicron transistor-level delay model. ICCAD 1998: 551-556
1987
1		Pierluigi Civera, F. Maddaleno, Gianluca Piccinini, Maurizio Zamboni: An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. ISCA 1987: 117-126

Coauthor Index

1	M. Addino	[18]
2	Mario R. Casu	[11] [13] [16] [17] [18] [20] [21] [22] [23]
3	Pierluigi Civera	[1]
4	Pasquale Cocchini	[2]
5	Marco Crepaldi	[22] [23]
6	Marco Delaurenti	[6] [7] [9]
7	Mariagrazia Graziano (M. Graziano)	[6] [7] [9] [10] [13] [16] [17] [20] [21] [22] [23]
8	F. Maddaleno	[1]
9	Maurizio Martina	[14] [15] [19]
10	Guido Masera	[3] [4] [5] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
11	M. Mazza	[12]
12	Andrea Molino	[19]
13	Massoud Pedram	[2]
14	Gianluca Piccinini	[1] [2] [3] [4] [5] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
15	M. M. Prono	[13]
16	Federico Quaglio	[19]
17	M. Ruo Roch	[3] [5] [8]
18	Massimo Ruo Roth	[4]
19	Fabrizio Vacca	[14] [19]
20	F. Viglione	[8] [12]