| 2002 |
|---|
| 6 | EE | Luc Séméria,
Renu Mehra,
Barry M. Pangrle,
Arjuna Ekanayake,
Andrew Seawright,
Daniel Ng:
RTL c-based methodology for designing and verifying a multi-threaded processor.
DAC 2002: 123-128 |
| 2000 |
|---|
| 5 | EE | Michael Münch,
Norbert Wehn,
Bernd Wurth,
Renu Mehra,
Jim Sproch:
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths.
DATE 2000: 624- |
| 1996 |
|---|
| 4 | EE | Renu Mehra,
Jan M. Rabaey:
Exploiting regularity for low-power design.
ICCAD 1996: 166-172 |
| 3 | EE | Paul E. Landman,
Renu Mehra,
Jan M. Rabaey:
An Integrated CAD Environment for Low-Power Design.
IEEE Design & Test of Computers 13(2): 72-82 (1996) |
| 2 | EE | Renu Mehra,
Lisa M. Guerra,
Jan M. Rabaey:
Low-power architectural synthesis and the impact of exploiting locality.
VLSI Signal Processing 13(2-3): 239-258 (1996) |
| 1995 |
|---|
| 1 | EE | Anantha P. Chandrakasan,
Miodrag Potkonjak,
Renu Mehra,
Jan M. Rabaey,
Robert W. Brodersen:
Optimizing power using transformations.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 12-31 (1995) |
