2006 |
23 | EE | Romanelli Lodron Zuim,
José T. de Sousa,
Claudionor José Nunes Coelho Jr.:
A fast SAT solver algorithm best suited to reconfigurable hardware.
SBCCI 2006: 131-136 |
22 | EE | Romanelli Lodron Zuim,
José T. de Sousa,
Claudionor José Nunes Coelho Jr.:
A Fast SAT Solver Strategy Based on Negated Clauses.
VLSI-SoC 2006: 110-115 |
2005 |
21 | | Victor Gonçalves,
José T. de Sousa,
Fernando M. Gonçalves:
A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits.
FPL 2005: 481-486 |
20 | EE | Ateet Bhalla,
Inês Lynce,
José T. de Sousa,
João Marques-Silva:
Heuristic-Based Backtracking Relaxation for Propositional Satisfiability.
J. Autom. Reasoning 35(1-3): 3-24 (2005) |
2004 |
19 | EE | C. J. Tavares,
C. Bungardean,
G. M. Matos,
José T. de Sousa:
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor.
FPL 2004: 344-353 |
18 | EE | Peter Y. K. Cheung,
George A. Constantinides,
José T. de Sousa:
Guest Editors' Introduction: Field Programmable Logic and Applications.
IEEE Trans. Computers 53(11): 1361-1362 (2004) |
2003 |
17 | | Peter Y. K. Cheung,
George A. Constantinides,
José T. de Sousa:
Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings
Springer 2003 |
16 | EE | Ateet Bhalla,
Inês Lynce,
José T. de Sousa,
João P. Marques Silva:
Heuristic-Based Backtracking for Propositional Satisfiability.
EPIA 2003: 116-130 |
15 | EE | A. Parreira,
João Paulo Teixeira,
A. Pantelimon,
Marcelino B. Santos,
José T. de Sousa:
Fault Simulation Using Partially Reconfigurable Hardware.
FPL 2003: 839-848 |
14 | EE | Ateet Bhalla,
Inês Lynce,
José T. de Sousa,
João P. Marques Silva:
Heuristic Backtracking Algorithms for SAT.
MTV 2003: 69-74 |
2002 |
13 | EE | N. A. Reis,
José T. de Sousa:
On Implementing a Configware/Software SAT Solver.
FCCM 2002: 282-283 |
12 | EE | José T. de Sousa,
Fernando M. Gonçalves,
Nuno Barreiro,
João Moura:
DARP - A Digital Audio Reconfigurable Processor.
FPL 2002: 556-566 |
2000 |
11 | EE | José T. de Sousa,
Vishwani D. Agrawal:
Reducing the Complexity of Defect Level Modeling Using the Clustering Effect.
DATE 2000: 640-644 |
10 | | Miron Abramovici,
José T. de Sousa:
A SAT Solver Using Reconfigurable Hardware and Virtual Logic.
J. Autom. Reasoning 24(1/2): 5-36 (2000) |
1999 |
9 | EE | Miron Abramovici,
José T. de Sousa,
Daniel G. Saab:
A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware.
DAC 1999: 684-690 |
8 | EE | Miron Abramovici,
José T. de Sousa:
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware.
FCCM 1999: 306-307 |
7 | | José T. de Sousa:
On Defect-Level Estimation and the Clustering Effect.
VLSI 1999: 257-268 |
1997 |
6 | EE | José T. de Sousa,
Peter Y. K. Cheung:
Improved diagnosis of realistic interconnect shorts.
ED&TC 1997: 501-505 |
5 | EE | José T. de Sousa,
Peter Y. K. Cheung:
Diagnosis of Boards for Realistic Interconnect Shorts.
J. Electronic Testing 11(2): 157-171 (1997) |
1996 |
4 | EE | José T. de Sousa,
Fernando M. Gonçalves,
João Paulo Teixeira,
Cristoforo Marzocca,
Francesco Corsi,
Thomas W. Williams:
Defect level evaluation in an IC design environment.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1286-1293 (1996) |
1994 |
3 | | José T. de Sousa,
Fernando M. Gonçalves,
João Paulo Teixeira,
Thomas W. Williams:
Fault Modeling and Defect Level Projections in Digital ICs.
EDAC-ETC-EUROASIC 1994: 436-442 |
1992 |
2 | | M. Saraiva,
P. Casimiro,
Marcelino B. Santos,
José T. de Sousa,
Fernando M. Gonçalves,
Isabel C. Teixeira,
João Paulo Teixeira:
Physical DFT for High Coverage of Realistic Faults.
ITC 1992: 642-651 |
1991 |
1 | | José T. de Sousa,
Fernando M. Gonçalves,
João Paulo Teixeira:
IC Defects-Based Testability Analysis.
ITC 1991: 500-509 |