| 2006 |
|---|
| 5 | EE | Pierluigi Daglio:
A complete and fully qualified design flow for verification of mixed-signal SoC with embedded flash memories.
DATE Designers' Forum 2006: 94-99 |
| 2005 |
|---|
| 4 | EE | Carlo Roma,
Pierluigi Daglio,
Guido De Sandre,
Marco Pasotti,
Marco Poles:
How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results.
ISQED 2005: 107-112 |
| 2004 |
|---|
| 3 | EE | Pierluigi Daglio,
David Iezzi,
Danilo Rimondi,
Carlo Roma,
Salvatore Santapa:
Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components.
DATE 2004: 336-337 |
| 2003 |
|---|
| 2 | EE | Pierluigi Daglio,
Carlo Roma:
A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies.
DATE 2003: 20274-20279 |
| 2001 |
|---|
| 1 | EE | Pierluigi Daglio,
M. Araldi,
M. Morbarigazzi,
Carlo Roma:
A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies.
ISQED 2001: 451-455 |
