| 2008 |
|---|
| 9 | EE | Saibal Mukhopadhyay,
Rahul M. Rao,
Jae-Joon Kim,
Ching-Te Chuang:
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.
ISCAS 2008: 384-387 |
| 8 | EE | Aditya Bansal,
Jae-Joon Kim,
Keunwoo Kim,
Saibal Mukhopadhyay,
Ching-Te Chuang,
Kaushik Roy:
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.
VLSI Design 2008: 125-130 |
| 7 | EE | Amlan Ghosh,
Rahul M. Rao,
Jae-Joon Kim,
Ching-Te Chuang,
Richard B. Brown:
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit.
VLSI Design 2008: 143-149 |
| 6 | EE | Niladri Narayan Mojumder,
Saibal Mukhopadhyay,
Jae-Joon Kim,
Ching-Te Chuang,
Kaushik Roy:
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.
VTS 2008: 101-106 |
| 2007 |
|---|
| 5 | EE | Saibal Mukhopadhyay,
Keunwoo Kim,
Jae-Joon Kim,
Shih-Hsien Lo,
Rajiv V. Joshi,
Ching-Te Chuang,
Kaushik Roy:
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.
Microelectronics Journal 38(8-9): 931-941 (2007) |
| 2006 |
|---|
| 4 | EE | Ik Joon Chang,
Jae-Joon Kim,
Kaushik Roy:
Robust level converter design for sub-threshold logic.
ISLPED 2006: 14-19 |
| 2005 |
|---|
| 3 | EE | Saibal Mukhopadhyay,
Keunwoo Kim,
Jae-Joon Kim,
Shih-Hsien Lo,
Rajiv V. Joshi,
Ching-Te Chuang,
Kaushik Roy:
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
ISQED 2005: 410-415 |
| 2 | EE | Chris H. Kim,
Jae-Joon Kim,
Saibal Mukhopadhyay,
Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.
IEEE Trans. VLSI Syst. 13(3): 349-357 (2005) |
| 2003 |
|---|
| 1 | EE | Chris H. Kim,
Jae-Joon Kim,
Saibal Mukhopadhyay,
Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device and architecture considerations.
ISLPED 2003: 6-9 |
