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Joel Silberman

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2007
7EEBrian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata: Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM Journal of Research and Development 51(5): 529-544 (2007)
2005
6 Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman: The circuit design of the synergistic processor element of a CELL processor. ICCAD 2005: 111-117
5EEShivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman: Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor. ISQED 2005: 54-58
4EEOsamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman: Power-Conscious Design of the Cell Processor's Synergistic Processor Element. IEEE Micro 25(5): 10-18 (2005)
3EEToru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara: Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. IEEE Micro 25(5): 30-38 (2005)
2000
2EEStephen D. Posluszny, N. Aoki, David Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia: "Timing closure by design, " a high frequency microprocessor design methodology. DAC 2000: 712-717
1998
1EEDavid F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin G. Stawiasz: High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS 1998: 234-238

Coauthor Index

1N. Aoki [2]
2Shigehiro Asano [7]
3Toru Asano [3]
4David Boerstler [2]
5Daniel A. Brokenshire [7]
6Russ Cook [6]
7Scott R. Cottier [3] [4] [6]
8P. Coulman [2]
9Sang H. Dhong [1] [2] [3] [4] [6] [7]
10James Dieffenderfer [5]
11Brian K. Flachs [2] [4] [6] [7]
12Gilles Gervais [7]
13Akiyuki Hatakeyama [7]
14David F. Heidel [1]
15Koji Hirairi [6] [7]
16H. Peter Hofstee [1] [2] [7]
17Michael Immediato [1]
18Eiji Iwata [7]
19Atsushi Kawasumi [3] [6] [7]
20Roy Kim [7]
21N. Kojima [2]
22Ohsang Kwon [2]
23Tien Le [7]
24K. Lee [2]
25Jens Leenstra [7]
26John S. Liberty [7]
27Peichun Liu [7]
28D. Meltzer [2]
29Brad W. Michael [7]
30Silvia M. Müller [7]
31Hiroaki Murakami [6] [7]
32Takaaki Nakazato [3]
33Hiromi Noro [6] [7]
34Kevin J. Nowka [1] [2]
35Hwa-Joon Oh [6] [7]
36S. Onish [6]
37Shoji Onishi [7]
38J. Park [2]
39Sanjay B. Patel [5]
40J. Peter [2]
41Mohammad Peyravian [7]
42Juergen Pille [6] [7]
43Stephen D. Posluszny [2]
44Kevin G. Stawiasz [1]
45Shivakumar Swaminathan [5]
46Osamu Takahashi [2] [3] [4] [6] [7]
47VanDung To [7]
48Paul G. Villarrubia (Paul Villarrubia) [2]
49Yukio Watanabe [7]
50Michael White [3]
51Naoka Yano [7]
52Suksoon Yong [7]
53Hiroshi Yoshihara [3]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)