| 2005 |
|---|
| 5 | EE | Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Debjyoti Ghosh,
Kaushik Roy:
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.
ISQED 2005: 453-458 |
| 4 | EE | Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Debjyoti Ghosh,
Saibal Mukhopadhyay,
Kaushik Roy:
Low-power scan design using first-level supply gating.
IEEE Trans. VLSI Syst. 13(3): 384-395 (2005) |
| 2004 |
|---|
| 3 | EE | Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Saibal Mukhopadhyay,
Debjyoti Ghosh,
Kaushik Roy:
A Novel Low-Power Scan Design Technique Using Supply Gating.
ICCD 2004: 60-65 |
| 2 | EE | Debjyoti Ghosh,
Swarup Bhunia,
Kaushik Roy:
A Technique to Reduce Power and Test Application Time in BIST.
IOLTS 2004: 182-183 |
| 2003 |
|---|
| 1 | EE | Debjyoti Ghosh,
Swarup Bhunia,
Kaushik Roy:
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.
DFT 2003: 191-198 |
