| 2009 |
|---|
| 3 | EE | R. Venkatraman,
R. Castagnetti,
Andres Teene,
Benjamin Mbouombouo,
S. Ramesh:
Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.
ISQED 2009: 27-32 |
| 2005 |
|---|
| 2 | EE | R. Castagnetti,
R. Venkatraman,
B. Bartz,
C. Monzel,
T. Briscoe,
Andres Teene,
S. Ramesh:
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.
ISQED 2005: 193-196 |
| 1 | EE | Andres Teene,
Bob Davis,
R. Castagnetti,
J. Brown,
S. Ramesh:
Impact of Interconnect Process Variations on Memory Performance and Design.
ISQED 2005: 694-699 |
