| 2005 |
|---|
| 9 | EE | Subhrajit Bhattacharya,
John A. Darringer,
Daniel L. Ostapko,
Youngsoo Shin:
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost.
ISQED 2005: 482-487 |
| 2004 |
|---|
| 8 | EE | Howard Chen,
Daniel L. Ostapko:
Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis.
PATMOS 2004: 809-818 |
| 2001 |
|---|
| 7 | EE | Jin-fuw Lee,
Daniel L. Ostapko,
Jeffery Soreff,
C. K. Wong:
On the Signal Bounding Problem in Timing Analysis.
ICCAD 2001: 507-514 |
| 1984 |
|---|
| 6 | | Daniel L. Ostapko:
A Mapping and Memory Chip Hardware which Provides Symmetric Reading/Writing of Horizontal and Vertical Lines.
IBM Journal of Research and Development 28(4): 393-398 (1984) |
| 1981 |
|---|
| 5 | | Se June Hong,
Daniel L. Ostapko:
A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks.
IEEE Trans. Computers 30(5): 356-358 (1981) |
| 1979 |
|---|
| 4 | | Daniel L. Ostapko,
Se June Hong:
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's).
IEEE Trans. Computers 28(9): 617-627 (1979) |
| 1975 |
|---|
| 3 | | Se June Hong,
Daniel L. Ostapko:
Codes for Self-Clocking, AC-Coupled Transmission: Aspects of Synthesis and Analysis.
IBM Journal of Research and Development 19(4): 358-365 (1975) |
| 1974 |
|---|
| 2 | | Se June Hong,
Robert G. Cain,
Daniel L. Ostapko:
MINI: A Heuristic Approach for Logic Minimization.
IBM Journal of Research and Development 18(5): 443-458 (1974) |
| 1 | | Daniel L. Ostapko,
Se June Hong:
Generating Test Examples for Heuristic Boolean Minimization.
IBM Journal of Research and Development 18(5): 459-464 (1974) |
